China’s Tau Scaling Breakthrough Just Made ASML Obsolete

Hinzugefügt: 2026-05-27

[00:00:00]A single machine, one machine, one company, one country, $380 million per unit. The United States, the Netherlands, and Japan decided that whoever controlled that machine controlled the future of AI, military hardware, and the global economy. For 7 years, it worked. Then, on May 25th, 2026, a woman walked onto a stage in Shanghai and retired the foundational principle the entire chip industry had operated under for 60 years. You heard that right. The metric the entire Western sanctions regime was built on, replaced in a single presentation. And that is just the beginning. If one announcement unraveling 7 years of the most sophisticated export control architecture in history sounds worth understanding, hit a quick like and subscribe. By the end of this video, you are going to understand exactly how China built a road to the same destination while every chip point in the world watched the other road.

[00:01:03]Chapter 1, the most expensive choke point ever built. To understand why May 25th matters, you need to understand what was supposed to make it impossible.

[00:01:13]Every modern chip is built by printing microscopic circuit patterns onto silicon. Think of it like a photocopier, except instead of copying a document onto paper, you are copying a circuit pattern onto silicon using light. The smaller the wavelength of light, the smaller the transistors. The smaller the transistors, the faster the chip. That is Moore's law. Shrink the transistor, improve the chip, repeat every 2 years.

[00:01:42]Eventually, chipmakers hit a wall. The features they needed became smaller than the wavelength of conventional light, like painting a portrait with a brush wider than the canvas. They needed extreme ultraviolet light, light at a wavelength of 13.5 nanometers, 1/10,000 the width of a human hair. Producing it requires a tin droplet the size of a grain of sand struck twice by a laser and exploding into plasma. The light captured by mirrors polished to atomic smoothness, projected onto silicon with nanometer precision. One company figured out how to build that machine commercially. ASML in Eindhoven, the Netherlands, [music] drew on over 5,000 suppliers across allied nations. ASML's most advanced extreme ultraviolet EUV machine cost $380 million.

[00:02:38]That is more than three of the world's most advanced fighter jets. No second source, no competitor within a decade of matching it. If you cannot get the machine, you cannot print features [music] below 7 nanometers. Washington understood this with surgical precision.

[00:02:55]From 2019 through 2022, >> [music] >> the United States pressured the Dutch government to deny ASML export licenses [music] to China. The Netherlands complied. Japan followed. The logic was elegant. Find the one irreplaceable node in the manufacturing chain [music] and put your hand over it. One company, one machine, one choke point. Now, here's the part most analysts never asked. The entire architecture, >> [music] >> seven years of allied coordination and billions in enforcement, rested on one assumption. That transistor size was the correct measure of chip performance.

[00:03:33]That the only road to a better chip ran through Eindhoven. Nobody asked what happened if someone built a different road. That question had already been answered quietly in commercial production by the one company everyone assumed was trapped.

[00:03:49]Chapter two. The woman who changed the question. Her name is He Tingbo. And [music] if you have never heard it, that is exactly the point. In the West, the semiconductor conversation has centered on TSMC, Nvidia, Intel, ASML.

[00:04:05]He Tingbo has been working in a different conversation. She is the president of HiSilicon, Huawei's semiconductor division, the engineer her colleagues call the architect of China's chip independence. [music] Her work was not the kind that releases.

[00:04:21]It was the kind that generates results first and announcements [music] second.

[00:04:25]On May 25th, she stood at the IEEE International Symposium on Circuits [music] and Systems in Shanghai, the arena where the global engineering community tests ideas against the hardest scrutiny.

[00:04:38]>> [music] >> He Tingbo chose that stage deliberately.

[00:04:41]Think about what it means to replace a unit of measurement, >> [music] >> not improve it, replace it. Imagine the entire construction industry measured buildings in feet for a century. [music] Every regulation, every blueprint written in feet. Then someone stood up and said the relevant unit was never feet. It was load-bearing capacity per square inch, and buildings rated highly in feet, but poorly in load capacity were actually inferior. That is the scale, not a better chip, a better way of deciding what better means. The Tao scaling law argues the correct measure of chip performance is not transistor size. It is how quickly a signal travels through the entire computing stack, from transistor switching through wiring, architecture, memory, packaging, and [music] data center communication, the full journey. Not the size of the door, the speed of everything moving through the building. Here is what most people get wrong immediately. This is not theoretical reframing. Signal propagation delay is a real, measurable, physical quantity. Transistor for was a useful proxy for it until advanced nodes where shrinking the transistor stopped improving the full signal journey automatically. Optimizing directly for tau unlocks gains. [music] The geometry first approach leaves entirely on the table. The sanctions were not wrong about ASML.

[00:06:04]They were wrong about what ASML's advantage actually represented. This was not a theory presented in Shanghai. The chips already existed. She was formalizing [music] a framework already proven in the field, but understanding what tau scaling physically does to a chip is where this [music] gets difficult to believe.

[00:06:23]Chapter 3, what tau scaling [music] actually does. Picture a city, a proper city with highways, side streets, and a thousand intersections. You need to move a message from one side to the other as fast as possible. For 60 years, the chip industry's answer was >> [music] >> make the city smaller. Shorter distances mean faster travel. Logical. Correct enough to work, but a smaller city is not automatically a faster city. Shrink the roads too aggressively and you create congestion. Reduce the lane width below a certain point and friction costs you more time than the shorter [music] distance saves. At 7 nanometers and below, the chip industry has been living inside that breakdown. Signal propagation delay, tau, is the time an electrical signal takes from origin to destination. Every nanometer of wiring adds resistance. Every junction adds capacitive load, electrical drag, like pushing a message through increasingly thick air. And here is the core insight.

[00:07:24]The interconnect wiring, not the transistor, is frequently the dominant source of delay in a modern chip. You heard that right. The thing slowing your chip down is often the wire, not the transistor. Now, here is the part that blows people's minds. EUV lithography shrinks transistors brilliantly, but the wiring connecting them does not scale as cleanly. At advanced nodes, wires become so narrow their resistance rises sharply, and adjacent wires start interfering with each other. You spent $380 million printing smaller transistors, and the wires are partially eating the gain. Here is the brutal catch the geometry-first framework never had to confront. On a 7-nm node, redesign architecture to minimize signal path length and reduce interconnect resistance, and you recover performance.

[00:08:18]A raw node comparison says should not exist. The transistors are not smaller, but the signals move faster, and faster signals mean more computational work per clock cycle. Huawei's modeling, presented at IEEE [music] with production data, projects that a chip optimized under tau scaling on a 7-nm process can achieve signal performance equivalent to what the industry calls a 1.4-nm node, TSMC's target, reached at over $1 billion per chip design. Huawei's path requires no EUV machine. The mechanism that makes that physically real is an architecture unlike anything the chip industry has built before. [music] Chapter 4: Logic Folding, the architecture that breaks the flat rule.

[00:09:06]Take a piece of paper, lay it flat, draw the most complex map you can imagine.

[00:09:11]Every road, every building, every connection in a major city on one sheet.

[00:09:18]The roads start crossing in confusion.

[00:09:20]Connections that should be close end up far apart. You run out of room not because the information does not fit, but because two dimensions is the wrong shape for the problem. That is the constraint every chip designer in history has worked [music] inside since the first integrated circuit in the 1950s, chip architecture has been planar, flat. Logic circuits laid across [music] a single horizontal plane. Every tool and methodology built around that flatness as an immovable given. Logic folding throws out the [music] given. If related circuits end up physically separated on a flat layout, forcing [music] signals through long horizontal distances, the solution is to stop laying circuits horizontally and start stacking them vertically. Not stacking whole chips, which the industry [music] already does with memory. Stacking the logic circuits themselves. Circuits that communicate [music] constantly placed directly above and below each other, rather than beside each other across a plane. A connection requiring hundreds of micrometers of horizontal wiring now travels a fraction of that distance vertically. The city did not get smaller. It got taller. And a taller city moves [music] messages faster than a flat one of the same footprint. Here is what makes this incredibly exciting.

[00:10:39]Vertical stacking does not just shorten signal paths. It changes the density equation entirely. More capability in the same silicon footprint. Not by shrinking transistors, >> [music] >> but by using the vertical dimension a planar layout left completely empty.

[00:10:54]Now, here's [music] the detail engineers have quietly wrestled with for years.

[00:10:59]The industry has known since the 1980s that vertical stacking could improve [music] density. The reason it stayed theoretical is thermal management.

[00:11:08]Concentrated heat throttles, [music] degrades, and eventually destroys chips.

[00:11:12]That thermal wall kept three-dimensional [music] logic integration in research papers for four decades. Huawei claims logic folding solves it. The evidence is not [music] theoretical. The chips are in production. The thermal wall that blocked this for 40 years has, by the data on record, been crossed.

[00:11:32]Chapter [music] 5. the numbers Huawei put on record. Precise numbers are the difference between a claim and a proof.

[00:11:38]He, Tingbo's IEEE presentation, >> [music] >> committed to figures specific enough to be independently tested. Start with transistor density. Logic folding [music] delivers 238 million transistors per square millimeter on Huawei's existing 7 [music] nanometer process, roughly the population of Brazil packed onto a surface [music] the size of your thumbnail, 238 million times over, a 53.5% [music] increase over conventional planar architecture, more than half again as many transistors, same process, no EUV machine. [music] Here is what makes that extraordinary. TSMC's 2 nanometer process, >> [music] >> the most advanced in mass production anywhere today, achieves approximately 180 million transistors per square [music] millimeter. Huawei's logic folding on a node four generation older produces a higher figure. You heard that right. A 7 nanometer chip with logic folding packs more transistors [music] per square millimeter than TSMC's 2 nanometer flagship. Here is the detail that puts everything into perspective.

[00:12:45]The power efficiency gain is 40% in AI infrastructure, where data centers consume as much electricity as mid-sized cities, 40% is not a footnote. It [music] is an infrastructure revolution.

[00:12:58]The United States restricted Nvidia exports to limit China's AI training capacity. [music] Large model training requires enormous computational and electrical power simultaneously. A 40% domestic efficiency [music] gain offsets both constraints at once. The sanctions were fighting on two fronts. Logic folding [music] advances on both. Clock speed is 3.1 GHz, a 12.7% increase over the baseline process, sitting firmly in competitive [music] processor territory paired with the density and efficiency gains, the combined performance [music] profile is categorically different from what a raw node comparison predicts. The first Kirin chips carrying logic folding launch in autumn 2026.

[00:13:40]By 2031, [music] Huawei projects density equivalent to TSMC's 1.4 nanometer process, the same target TSMC reaches by physically shrinking transistors at over 1 billion dollars per chip design. Two roads, two [music] price tags, same destination within three years of each other, but the most extraordinary part of this story is not the numbers. It is when those numbers started being real.

[00:14:06]Chapter 6, 381 chips before anyone was watching. There is a kind of confidence that only comes from one source, >> [music] >> not from a theory, not from a prototype, from having already done the thing repeatedly at scale in products real people bought. Think about an iceberg.

[00:14:24]The announcement, the framework, the IEEE stage, that is the part above the waterline. The mass that made it possible sits entirely below. By the time an iceberg is visible, the underwater structure is already complete. The number is [music] 381.

[00:14:41]That is how many chips had already been mass produced using Tao scaling principles before the IEEE [music] presentation. 381 distinct designs, not lab samples, but commercial chips generating yield data and performance data across millions of units. More chip designs than most semiconductor companies produce in a decade. Here is the part nobody talks about. The Tao scaling framework did not emerge as a response to EUV denial. Development ran in parallel with the sanctions escalation alongside it, not chasing it.

[00:15:14]While Washington tightened controls in 2022 and 2023, Huawei was already years into validating the framework [music] that would make those controls structurally beside the point. Shanghai was a disclosure moment. The breakthrough had already happened. Now, here is what makes this incredibly significant. Western [music] analysis focused almost entirely on process node.

[00:15:37]Could China reach 5 nanometers? Could SMIC yield advanced nodes at volume? It is [music] the analytical equivalent of tracking how fast someone climbs a ladder while they quietly build an elevator next door. Accurate, [music] just measuring the wrong thing. The Ascend 950 for 2026 already incorporates three-dimensional [music] stacking, the foundational techniques logic folding builds on. The Ascend 990, projected for 2030, fully integrates logic folding, placing it on a performance trajectory. [music] The sanctions were mathematically designed to make impossible on a domestic node. [music] 381 chips, not evidence of a single capability, evidence [music] of a methodology. A disciplined long-horizon development program [music] that never announced itself. It just kept shipping products quietly for years while every eye in the industry watched the checkpoints [music] on the geometry road.

[00:16:35]Chapter 7, the road that was never on the map. To understand what the Tayu scaling law does to [music] the sanctions architecture, you need to understand what a choke point strategy is.

[00:16:45]>> [music] >> A choke point is not a ban. A ban tries to stop everything. A choke point is more elegant and more fragile. [music] It finds the single irreplaceable node and applies pressure there. You do not need to stop every road. You only need to control the one road everyone [music] must use. Think about a canal, not a river, a canal. A river [music] has tributaries and alternate routes. A canal is engineered narrowness, one channel connecting two points. Nothing else connects as efficiently. [music] Control the canal, control the trade.

[00:17:17]The ASML EUV machine was the Panama Canal of the semiconductor world. One channel, engineered irreplaceability, allied consensus [music] as the lock.

[00:17:27]The Taeyou scaling law did not blow up the canal. It made the destination reachable by air. Here is the [music] strategic verdict. The ASML high NA machine costs $380 million, more than three advanced fighter jets.

[00:17:42]Over 5,000 allied suppliers feed its production. [music] It takes over a year to install. It represents decades of engineering. No Chinese company and no black market was going to replicate in time. Washington [music] did not build a flawed strategy.

[00:17:56]It built the most sophisticated export control architecture in the history [music] of technology competition. And the Taeyou scaling law did not defeat [music] it. It rendered it an answer to a question that is no longer the primary question.

[00:18:11]Now, here's the part that puts everything into [music] perspective.

[00:18:14]Export controls rest on one fixed assumption, that the metric being controlled today governs the competition [music] tomorrow. The ASML controls were written in the grammar of Moore's Law.

[00:18:25]When He Tingbo replaced that grammar, she did not just announce a chip architecture. She announced the obsolescence of the classification system [music] seven years of allied effort had been built around. The implications reach beyond semiconductors. This is the first time a sanctioned party responded to a choke point not by replicating the controlled technology or obtaining it through back channels, but by redefining what its advantage actually means.

[00:18:51][music] Not evasion, not replication, redefinition. That forces one new question on every strategist [music] building the next choke point across advanced materials, quantum computing, and biotechnology. What happens if the other side builds a framework [music] that makes your road secondary? The ASML machine still works. TSMC's [music] geometric scaling program in human history. What [music] changed is that the assumption of irreplaceability now has a credible production validated challenge. 381 [music] chips are already in the field. Consumer devices in autumn 2026.

[00:19:32]A documented trajectory to 1.4 nanometer equivalents by 2031. [music] The road the world agreed was the only road turned out to have always been one road.

[00:19:42]The country that spent six years quietly building [music] a different one just arrived at the same destination. The map every strategist navigated from never showed the other road [music] because the other road was never supposed to exist. It does now.

[00:19:57]If this changed how you think about technological competition between great powers, >> [music] >> hit that like button and subscribe so you never miss what comes next. Now I want to hear from you in the comments.

[00:20:07][music] Do you think the TIU scaling law genuinely ends the semiconductor choke point era? Or do you think the West will find a new irreplaceable [music] node fast enough to matter? Two camps. Make your case.