Course: Systemverilog Design 3 : L4.1 : Writing General Components in RTL Design - Part A

[00:00:00]now you will learn how to write a complete system verilog synthesizable code to design and interconnect so before going into the actual design in this session you will be learning to write few general components so in every system will have descend there are few modules or components which will come multiple times in a design and or another way if you decode any complex design into some simple uh system buildup modules those should be composed of a few multiplexes few flip flops and a few other simple circuits so these are called the general components and you need to write your own code for your general components if it is not really available readily so if you are working in a company this will be available in the company or the the tool companies will provide this library library components otherwise you need to write these components from scratch so here you learn how to write those components so we'll be learning how to write a asynchronous resettable flow and asynchronous resettable flop with an enable signal then uh how to write a multiplexer and d multiplexer also finally you'll be learning how to write fp4 so these are the basic building blocks of almost every system by log circuits digital circuits so the first one is a d flip flop with asynchronous reset so a simple flop is an asynchronous reset so this is the code module uh default passing reset which is parameterized with the type of logic 7.0 and your inputs are the clock reset and the dn and the output is d out and the input and output are of type which is passed as a parameter it's the default value is logic 7 down to serum now the functionality of a flop is very simple since the flow piece of asynchronous reason whenever there is a reset assorted you need to reset the output value to zero and whenever there is a clock available you need to store the in din and store it and flop it out to the layout in the next clock so this is a code in system variable for that always at positive clock or negative edge of reset so here we are considering the reset as a negative reset this always a positive edge of clock or negative just reset uh within a beginning you are writing the code here so if reset is equal to x or which is unknown then the output will be again unknown and else if the reset is um zero that is if three c is asserted then d out will be zero which will be reset the output value will be reset to zero and if there is if any none of these are there and uh if the clock is again x your d out will go x and if there is no reset or clock going to x or nor is it assorted then your diode will be equal to dn in the next positive jeff cloud so that is accomplished by using the non-blocking assignment statement which is less than or equal to so you can see that all your statements are assigned with a non-blocking assignment less than or equal to and also you might have noticed that i have added a hash one delay here in this flow this is to get the correct simulation behavior when we consider the setup and hold time or the other timing passing in the real flip flop this is how you model a flip flop uh which will store a type of logic 7.0 which is of eight bit fight and you can change the type or the width of the flip flop by changing the parameter while instantiating this particular flip flop now this flip flop doesn't have any um enable signal next we'll be learning how to implement an uh flip flop enable signal so the code is almost same you will be passing one more input to this module which is the enabled and if any of the clock or enable is going x then your d out will be again x or unknown and if not if there is enabled then you will change the output value to the input value so this is a change from the previous code you can see that here by default if none of these conditions are asserted your d out will be equal to dn in the next clause but here if none of these conditions are then there and if enable signal is asserted then they have to be assigned to d in the next clock so this is how we implement a flip flop with enable signal now you should use a flow with enable signal whenever it is possible the reason is if you had a symbol flop without enabled signal that flop will be powered or triggered on every positive edge of clock and if your input is not really changing on every clock positive or just a clock this uh power triggering or power power supply to this flop is unwanted or it is faster so if you can use an enable signal which will enable the flop only when there is a change in the input then it will save a lot of power so it is recommended to use an enable signal for almost of the all the flops especially when you want to flop a lot of signals