Rapidus, a Japanese semiconductor company founded in 2022 with $65 billion in government backing and IBM's 2nm gate-all-around transistor technology, has achieved transistor density (237.31 million/mm²) matching TSMC's N2 process, but faces the enormous challenge of scaling from pilot production to high-volume manufacturing, where TSMC's decades of accumulated process knowledge and yield optimization remain critical competitive advantages.
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The Japanese Factory That Could End TSMC's Monopoly
Added:There is one company that makes the chips that run the world. Not one of the best companies. Not the market leader among several competitors. One company with more than 90% of the market for the most advanced semiconductor manufacturing on Earth. Everything that defines the AI era, every Nvidia GPU, every Apple processor, every custom AI accelerator powering the data centers that run your life, begins as silicon wafers processed in a cluster of factories in Taiwan. That concentration is the most dangerous single point of failure in the global technology supply chain, and every government in the world that depends on those chips knows it.
The United States knows it. That is why the CHIPS Act committed $52 billion to building semiconductor manufacturing on American soil. Japan knows it. That is why in a frozen industrial zone outside Chitose City in Hokkaido, the Japanese government has committed the equivalent of $65 billion to building a chip factory that 4 years ago did not exist.
The company is called Rapidus, and in July 2025, it successfully operated gate-all-around transistors for the world's most advanced 2-nanometer semiconductor process. In February 2026, it completed a funding round of 267.6 billion yen, $1.7 billion in a single round. In April 2026, Japan's Ministry of Economy, Trade, and Industry approved an additional 631.5 billion yen, pushing Japan's cumulative government investment in Rapidus to approximately 2.35 trillion yen. And the transistor density numbers published for Rapidus's 2-nanometer process, called 2HP, show 237.31 million transistors per square millimeter.
TSMC's N2, the most advanced chip manufacturing process in volume production anywhere on Earth, shows 236.17 million. A Japanese company founded in 2022 has matched TSMC's leading-edge density number on paper. I'm a chip design engineer and I've spent my career watching the semiconductor industry. I want to give you the honest version of what Rapidus actually is, what it has actually proven, and what it would actually take for it to matter. Because the gap between a transistor density number and a real chip factory that can compete with TSMC is enormous. And understanding that gap is the most important part of this story. Subscribe to the channel and let me show you.
Before we continue, I want to mention something I've been working on behind the scenes. Over the past several months, I've spent hundreds of hours researching AI infrastructure, semiconductors, data centers, power systems, supply chains, and the companies building the foundation of the AI economy. One thing I discovered is that most of the information exists in scattered pieces across earnings calls, industry reports, technical papers, government documents, company filings, and news sources. Understanding the complete picture requires putting all of those pieces together. That's why I created the AI infrastructure report 2027. Inside this 46-page report, you'll find the key data, industry analysis, infrastructure frameworks, company research, and long-term forecasts that took months to collect, organize, and synthesize into a single resource.
Instead of spending months digging through hundreds of sources yourself, you can access the complete research in one place. If you enjoy the deep dive analysis on this channel and want to go much deeper than what I can cover in a single video, you'll find the report linked in the description below.
Now, let's get back to today's story. To understand why Rapitas matters, you need to understand what happened to Japan's semiconductor industry. And that story is one of the most dramatic industrial declines in modern history. In 1988, Japan controlled 50% of the global semiconductor market.
Half of every chip made anywhere on Earth was made in Japan.
Japanese companies like NEC, Hitachi, Toshiba, Fujitsu, and Mitsubishi were the dominant forces in semiconductor manufacturing.
The country had built its post-war economic miracle partly on the strength of its electronics industry and the chips that powered it. Then, two things happened simultaneously. The US-Japan Semiconductor Agreement of 1986, signed to resolve trade friction, imposed restrictions on Japanese chip exports and guaranteed foreign companies a minimum 20% share of the Japanese market. And South Korea and Taiwan, with lower labor costs and aggressive government support, began building their own semiconductor industries. Over the following decade, Samsung emerged as a memory chip powerhouse. TSMC, founded in 1987 by Morris Chang, invented the pure play foundry model, making chips for other companies' designs rather than producing its own products. Japan's integrated device manufacturers, which designed and fabricated their own chips, could not compete on cost with TSMC's model and could not compete on memory density with Samsung. By 2010, Japan's global semiconductor market share had collapsed from 50% to around 10%. By 2020, it was below 10% and concentrated mostly in specialty applications and legacy nodes. The most advanced chips, the chips that define what AI can do, what smartphones can do, what data centers can do, were no longer made in Japan at all. This was not just an economic problem. It was a national security problem.
Japan's entire industrial economy, its automotive industry, its robotics sector, its telecommunications infrastructure, its defense technology, depends on advanced semiconductor chips.
And Japan was importing virtually all of those chips from Taiwan, South Korea, or the United States. The 2021 global chip shortage made this vulnerability viscerally clear.
When a COVID-driven supply chain disruption caused chip shortages across the global economy, Japan's automotive industry was hit particularly hard.
Toyota, which produces some of the most complex vehicles on Earth, was forced to cut production significantly because it could not get the chips it needed. For a country that had once dominated semiconductor manufacturing, depending on foreign suppliers for components that were now the foundation of its economy was intolerable. And then came the geopolitical dimension that made the dependence feel existential. Taiwan sits 90 mi from China. The Taiwan Strait is one of the most tense geopolitical flash points on the planet. China's stated position is that Taiwan is part of China, and that reunification is a matter of national policy. Any disruption to Taiwan's semiconductor manufacturing output, whether from military conflict, natural disaster, or political crisis, would be catastrophic for every country that depends on TSMC.
Japan, which sits geographically close to Taiwan and has its own complex history with China, understood this more acutely than almost any other country.
And the response was rapidest. In August 2022, eight of Japan's largest and most important industrial companies, Toyota, Sony, NTT, NEC, SoftBank, Denso, Kioxia, and MUFG Bank, formed a consortium with a single stated goal: build a 2-nanometer chip factory in Japan by 2027.
Not a legacy chip factory. Not a mature node facility. A leading-edge 2-nanometer factory capable of producing the most advanced chips on Earth.
The ambition was staggering.
There are exactly three companies in the world that can manufacture chips at the leading edge. TSMC, Samsung, and Intel Foundry.
Each of them has decades of accumulated manufacturing knowledge, hundreds of billions of dollars of invested capital, and workforces of tens of thousands of engineers with specialized expertise built over careers. Rapidus had none of that. It was starting from zero, but it had two things that no semiconductor startup in history had ever had simultaneously: unlimited government support and a technology license from IBM. IBM's role in this story is critical and largely underreported. IBM Research, based at the Albany Nanotech Complex in New York, developed 2-nanometer gate-all-around transistor technology and announced it in 2021.
IBM's 2-nanometer prototype chip demonstrated extraordinary density and power efficiency. But IBM has not been in the semiconductor manufacturing business for years. It sold its chip manufacturing operations in 2014. The Albany research facility produces prototype chips for research purposes, not commercial volumes. What Rapidus did was license IBM's 2-nanometer process technology for commercial manufacturing.
More than 100 Rapidus engineers were sent to Albany to learn the process directly from IBM's research team. The technology transfer was not a document handover. It was an immersive engineering education conducted over years with Rapidus engineers working alongside IBM researchers to deeply understand how the 2 nanometer gate all around process actually works at the physical level. This is the foundation that no semiconductor startup has ever had before. Rapidus is not trying 2 nanometer manufacturing from first principles. It is taking proven 2 nanometer research technology from one of the world's most respected research institutions and learning how to scale it into a production environment. The challenge is enormous, but the starting point is dramatically better than any other new entrant to this market has ever had. And the Japanese government, understanding what is at stake, has committed financial support at a scale that makes the CHIPS Act look measured.
The cumulative government investment in Rapidus has crossed 2 trillion yen.
Japan announced a further 1 trillion yen injection planned for 2026 and 2027 specifically. The total investment target for Rapidus to reach mass production is estimated at 5 trillion yen, $35 billion.
The Japanese government has taken an 11.5% voting stake in the company along with a golden share that gives the state veto power over major strategic decisions. This is not a commercial investment. It is a national security project structured as a company. The factory is being built in Chitose City in Hokkaido, Japan's northernmost main island. The location is not accidental.
Hokkaido has abundant cold water resources for chip manufacturing cooling systems, stable power supply, low seismic risk relative to other parts of Japan, and land available for the enormous facility footprint that an advanced semiconductor fab requires.
The IIM 1 facility, Rapidus' first integrated fab, began installing equipment in 2024 and powered up its pilot production line in April 2025.
And then, in July 2025, Rapidus announced the milestone that changed the trajectory of this story.
The successful operation of gate-all-around transistors for the 2-nanometer process. Not a simulation, not a theoretical result. Real transistors on real silicon, processed through real manufacturing equipment, working as designed. For a company that did not exist in 2021, this is an extraordinary technical achievement. The GAA transistor architecture, where the gate wraps around all four sides of the channel instead of three, is the most complex transistor structure ever put into commercial production.
TSMC only introduced GAA with its N2 node in late 2025.
Intel introduced it with its 18A process. Samsung introduced it earlier with its 3-nanometer GAA node, though with significant yield challenges.
Rapidus demonstrated working GAA transistors on the same timeline as TSMC's N2 production ramp, a company that started from scratch in 2022. Now, let's talk about the 2-nanometer supply crunch, because this is the market context that makes Rapidus' timing matter so much. TSMC's N2 process entered volume production in late 2025, and from the moment production began, it was effectively sold out. Every wafer TSMC can produce on N2 through 2026 has been claimed by existing customers.
Apple is taking more than half of the initial N2 capacity for its A-series processors. Nvidia, AMD, Qualcomm, and MediaTek have locked up the remainder.
If you are a chip company that wants to design and manufacture a 2-nanometer chip today, TSMC will tell you the queue extends into 2027 and beyond. And TSMC has raised its foundry prices by 5 to 10% across advanced nodes in 2026 because the demand for its manufacturing capacity vastly exceeds supply. This is the structural opening that every competitor to TSMC is trying to exploit. Samsung is producing 2-nanometer chips with its SF2 process, but yields are running around 50 to 60% significantly below TSMC's production efficiency. Samsung has customer commitments from Tesla for its 2-nanometer node and Qualcomm for Samsung specific products, but has struggled to attract broad customer adoption because yield variability makes planning difficult. Intel's 18A process is in high-volume manufacturing with improving yields, now targeting the external foundry market with a handful of confirmed customers. But Intel's 18A transistor density of 184 million transistors per square millimeter is meaningfully lower than TSMC's N2 at 236 million. Which brings us back to Rapidus's 237.31 million transistors per square millimeter.
If that number is accurate, and it comes from process design kit data shared with prospective customers rather than from verified independent measurement, Rapidus's 2HP process matches TSMC N2 density, not approaches it, matches it.
From a company that was founded four years ago. Here is where I need to be very precise because there is a critical difference between density specification and manufacturing reality. Transistor density is a specification derived from the process design rules. It tells you how many transistors you could theoretically pack into a square millimeter if you use the densest possible cell library and everything went perfectly. It is the theoretical ceiling, not the practical floor. What the density number does not tell you is yield, which is how many chips actually work after manufacturing. It does not tell you throughput, how many wafers per hour the fab can process. It does not tell you defect density, how many flaws per unit area the process generates. And it does not tell you process stability, whether the manufacturing parameters hold consistent across thousands of wafers over months of production. TSMC's superiority over every competitor is not fundamentally about having a higher density specification. TSMC achieves high density and high yield simultaneously at high volume. That combination, achieving the N2 specification number while running 80 or 90% yield across tens of thousands of wafers per month, is the real competitive advantage. And it took TSMC decades of incremental process development, equipment optimization, and engineering experience to achieve it.
Rapidus is nowhere near that production capability yet. Its IIM 1 facility is targeting 25,000 wafers per month when it reaches volume production in 2027 or 2028. TSMC's Taiwan fabs produce millions of wafers annually across all nodes with N2 capacity alone expected to scale to tens of thousands of wafers per month, and Rapidus's early yields on its pilot line are by necessity early-stage yields. Demonstrating that transistors work on a pilot line is not the same as demonstrating that a high percentage of complex system-on-chip designs manufactured on production equipment deliver acceptable performance. This is the honest picture. Rapidus has achieved something genuinely impressive. Working 2-nanometer GAA transistors from a standing start in under 4 years is not something that should have been possible. But, the distance between working transistors on a pilot line and a reliable high-volume foundry that companies would trust with their most critical chip designs is measured in years of additional engineering work.
So, why should anyone take Rapidus seriously as a competitor to TSMC? Three reasons. The first is the business model. TSMC makes its business on high-volume production of established chip designs. The economics of TSMC's model depend on producing enormous quantities of the same design with high yield. That model is perfectly suited to Apple's iPhone chip, which ships in hundreds of millions of units, or Nvidia's GPU, which ships in millions of units. But, there is an enormous and growing market for chips that do not need millions of units production runs.
AI inference chips designed for specific data center architectures, custom automotive chips, research institutions that need prototype silicon for new AI model architectures.
Defense applications that require small quantities of highly specialized chips.
For these customers, TSMC's model, where your design gets queued behind Apple's orders and waits for allocation on a production line optimized for different chip architectures, is not ideal.
Rapidus's approach is what it calls short TAT manufacturing, where TAT stands for turnaround time. Rather than batching wafers in large lots through a fixed process sequence, Rapidus processes each wafer individually. This adds cost per wafer compared to batch processing, but it dramatically reduces the time from chip design to silicon.
Where TSMC's cycle time from design tape out to receiving sample chips might be 3 to 6 months, Rapidus is targeting cycle times measured in weeks. For customers who are iterating on chip designs rapidly, AI companies experimenting with new architectures, automotive companies adapting chips for new vehicle platforms, that turnaround time reduction is worth significant cost premium. The second reason to take Rapidus seriously is its customer pipeline. Tenstorrent, the AI chip company led by CPU architecture legend Jim Keller, announced a contract with Rapidus for production of its next-generation RISC-V based AI chip.
Tenstorrent is backed by Hyundai, LG, and Samsung Electronics investment arm.
And its choice of Rapidus signals that serious AI chip companies are treating the Japanese foundry as a real manufacturing option, rather than a geopolitical vanity project. Rapidus is also working with Broadcom on IP and design kits, with Synopsys on EDA tools, and with Canon on chip trial runs. The design ecosystem is maturing. The third reason is geopolitical inevitability.
The diversification of advanced semiconductor manufacturing away from Taiwan's concentration is not a policy preference. It is a strategic necessity that every major economy has identified simultaneously.
The United States is building TSMC Arizona and Intel's next-generation fabs. Europe is building TSMC Dresden.
Japan is building Rapidus in Hokkaido.
Korea is expanding Samsung's international footprint. The logic is identical in every case. The risk of having 90% of the world's most advanced chip manufacturing in one politically vulnerable location is too large to accept, and the solution requires building new capacity somewhere by someone.
Rapidus is Japan's answer to that requirement, and the Japanese government has decided that the cost of building it, potentially $35 billion before reaching meaningful production volume, is acceptable compared to the cost of continued dependence. But here is the deep challenge that no amount of government funding can entirely solve.
Building a chip factory is not like building a power plant or a highway. The knowledge required to run a leading-edge semiconductor fab is not written in engineering manuals. It is embedded in the practice of thousands of engineers who have spent careers learning how materials behave at atomic scales, how process parameters interact across hundreds of manufacturing steps, how equipment ages and drifts and requires recalibration, how defects form and propagate and get suppressed. This knowledge is accumulated through years of production runs, failed experiments, and continuous improvement cycles.
TSMC's process engineers have been refining N2 production since risk production began in 2024. Every wafer they run teaches them something about defect sources, parameter optimization, and yield improvement. By the time Rapidus begins volume production in 2027 or 2028, TSMC will have 2 to 3 years of N2 production learning behind it, and TSMC will have already transitioned its frontier attention to A14, its angstrom-class process, and A13, the leading edge will have moved. Rapidus' chairman Tetsuro Higashi acknowledged this directly, saying Japan's advanced logic semiconductors are 10 to 20 years behind and that Rapidus is fortunate to have IBM providing GAA technology to compress that gap. That honesty is itself telling. The goal is not to immediately dethrone TSMC. The goal is to get Japan back into the game at leading edge manufacturing within this decade, rather than watching the gap compound for another 20 years. And there is one more dimension to this story that almost nobody is discussing. Because Rapidus is not building in isolation.
Japan's semiconductor strategy has two tracks running simultaneously. While Rapidus is building the leading edge frontier capability, TSMC is simultaneously building a second fab in Japan's Kumamoto prefecture in partnership with Sony and Denso, producing 3 nanometer chips for the Japanese automotive and consumer electronics market. This two-track approach is deliberate. The Kumamoto fab addresses immediate supply chain diversification for the chips Japan's existing industries need right now.
Rapidus addresses the long-term goal of building Japan's own leading edge capability for the AI era that is arriving. Together, these investments represent Japan's most significant industrial policy commitment since the post-war reconstruction. The country that invented the transistor and everything from Walkman to video game console, that once dominated global chip production, is attempting to rebuild that capability from a foundation that had almost entirely eroded. Whether Rapidus succeeds will depend on things that cannot be purchased with government funding. It will depend on whether the GAA process transferred from IBM scales reliably to production volumes. It will depend on whether Rapidus can attract and retain the engineering talent needed to run and improve a cutting-edge fab over years of operation. It will depend on whether the short TAT business model generates enough revenue to fund the continuous improvement that leading-edge manufacturing requires. But consider what failure would mean for the global semiconductor map. If Rapidus fails, Japan's leading-edge chip ambitions collapse for at least a decade. The country remains dependent on TSMC and Samsung for the chips its AI economy, its automotive industry, and its defense applications require.
The geopolitical risk that motivated the project in the first place intensifies.
And consider what success would mean.
A fourth leading-edge foundry.
A production base in a politically stable, geographically diverse location.
A business model that serves the custom chip market TSMC's volume economics cannot efficiently serve. Competition in the 2-nanometer market that gives chip designers alternatives to TSMC's pricing power. And proof that a country can rebuild semiconductor manufacturing from near zero with sufficient strategic commitment. TSMC built its position over 38 years. Rapidus is attempting to reach the frontier in five. The semiconductor industry has never seen anything like it. And the Hokkaido fab now has EUV machines installed, transistors working, and customers signed. The race has begun. If you enjoyed this video and want the deeper research behind it, check out the AI Infrastructure Report 2027 linked below. It brings together months of research, industry analysis, and 50 forecasts through 2030 in one place. Thanks for watching, and I'll see you in the next video.
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