Course: Systemverilog Design 3 : L2.1 : Writing Interface Definition

[00:00:00]interface and system reload when you declare a module you will be declaring the module with the list of ports that is coming into the module and going out to the module or in other ways you have to list out all the inputs and the outputs of the particular module in most of the cases this spot list will be repeated in multiple modules especially when you use different hierarchy of design and also in the test bench so in order to abstract all the signals or all the ports that is coming into a particular module system verilog added the new constructs called interface the interface constructs in system window was specifically created to encapsulate the communication between blocks and at its lowest level it is named bundle of nets for variable we will see more details in the next slides and you will be familiar with the x usage of interface interface declaration the declaration syntax is similar to that of a module declaration as you remember the module is declared the syntax module the keyword module then module name followed by the port list in the same way the interface is declared with the keyword interface followed by the interface name and within the brackets you will list out the ports to this interface or the inputs and outputs to this interface and the semicolon within the interface and interface keyboard you will define the interface functionality so in this example this interface is named with axi write address interface xawar added or intf and to this interface we are passing the inputs as clock and recent typically in every interface definition you will be passing the clock and reset signal as input to this interface next you can see these are the signals that is defined in an ix right address and with the appropriate dimension i have defined all the signals of simple logic items and they are not listed in the in the port list but they are just something similar to a local within this interface so they are simple logic items they are not either inputs or outputs now all the rules that is applicable for the module definition is also applicable for interface definition we can use parameters if you want and once you define an interface you need to create instance of that before you using them and here you can see that all the signals are defined as simple logic items but effectively when you use them in a module these signals will be either act as an input or act as an output so for example if you are if you are using this interface in in the duty where it where it is accepting data from an outside world then all the signals that wid address length up to this w port will be coming us input to this in input to this module so that they should be acting as input within this interface and uh also violet will be an input and the ready will be an output signal but but in the same way if you want if you wanted to drive those signals from the test bench then all the signals will be output in the test bench and this will be an input to the test bench so in order to define the direction there should be some mechanism in the interface declaration so to define the direction of these nets you need to define different module ports called mod port within the interface here is a complete interface declaration so interface followed by the interface name and if any parameters are that it is they're listed by using the a half symbol and the ports are listed then then all the signals in the interface are listed as the functional signals are listed as logics keywords and here i have defined two module ports or mod ports named as master and slave so when this interface is used in a master you can see that these signals the clock and reset will be always an input irrespective of whether it is a master or slave and all of the signals will behave differently so here the signals from aw id to add valid will be acting as output signals in a master and the ready will be an input to this master thus i have defined a module mode port named master by using the keyword mod port followed by a user defined name and within the bracket you will list down the direction of the signals so you just need to list down uh or define whether it is an input or output you don't need to again specify the the diameter here again because you have already specified the dimensions of the individual signals here thus you are saying that within this module mode port called master the signals clock and reset are input and all the signals from a w id to a w valid are outputs and again aw radius and input and in the same way when this interface is used in a slave you can see that all these signals will be uh should be acting as an input to the slave thus i have defined another module port called slave and here also the clock and resistor in uh signals are input signals and all the signals from wid to w violet are again input to a slave so they are defined as inputs or that the direction is defined as input and uh the ready is an output of the slave so its direction is specified as an output so this is an example of a complete interface declaration now you will see how to use this interface in your actual design so this was the interface declaration that we have seen in the previous line so this will be your duty and this is the testbench code you can see that in the duty code within the duty card port list itself we are listing out an interface here so here the x right address interface is listed and here it's direction need to be slave thus we are saying x right address interface dot slave mod port so this is a slave mod pod defined in this interface and its two handles are declared in the module parts thus x right address interface 1 and x right address interface 2 will be the handles of accelerated handles of this interface with mod module for direction slave and with this simple sentence you are able to list out two set of x interfaces to this module so if you are not using interface here you might want to list out all the signals expressly here twice and other thing is that there will be some modules within the top module and wherever you are passing this axis rights channels there are all the places you might want to distort all the signals specifically now in the design whenever you wanted to access signal within that interface you can access like x write address interface one without the signal name now in the test punch module when you create the instance of the module or the duty you have to pass out this instance of interfaces also thus here i have created an instance of the interconnect with the name interconnect one and i used a dot star here thus there should be a signal called clk and rst here in this module and also there should be an interface declaration with the same name here the exit wr adr indf is instantiated twice here with appropriate ports and when you drive this signals you need to drive them like interface dot the signal name thus say for example if you want to pass a particular w id to the first x right channel then then you should pass it like x a w are added here indf one dot awd is equal to the particular value so another point is when you create the instances you have to pass down the ports appropriately so here uh to this interface there are two signals past a spot so those signals you need to pass them uh when you create the instance of the interface interface is a very useful system with low constructs it will be very useful in when you create multiple modules and multiple hierarchy of modules and throughout in our example we will be using interface and you will be more familiar with them when you go through the examples