Course : Systemverilog Verification 5 : L13.2 : Example - Writing Coverage Module

[00:00:00]so i am using the eda playground overland simulator in order to enable functional coverage and see the functional coverage report you need to use the revera simulator and also you need to enable a run to do file so you should take this option run use run.do file and you should write a do file in your in your file area and also uh you can check the download file after an option in order to see the actual coverage report you can choose only one option between these two so before your code is compiled clean you may choose the open wave option and once your code is complete compile clean uh then you can use the download file option otherwise every time it will download the file whether there is an error or a note in the compilation and now you see the run.do file so you need to create a file called run.do and name it as run.do and you should write these options in that do file so here i'm using ubm test page so i'm passing it the um test name as the online simulation argument thus i'm giving this option otherwise uh you need to give all the vcm options here and also use these commands to enable coverage and between the files i'll be just browsing the files which are just relevant for the coverage analysis now we will see the duty so the duty name is interconnect this is a final duty its name is interconnect it has multiple sub units or sub modules in that and you can see that in the port level it has got five set of uh two set of x interfaces uh where every x interface has five subset of interface so there is an x right address interface write data right response and read address read data and ocp interface you can see that all these x interfaces are coming as two interface one and interface two thus there are two set of ax interfaces and we will see the interface definition in the file interface dot sv so these are the signals coming in every interfaces so we will be writing our points for few of these signals now in the test punch part this test punch is written in uvm so you don't need to go through all the other parts but you just focus on the part which is uh enabling functional coverage so in the final test bench module after declaring the necessary interfaces and you need to instantiate your interconnect module with the appropriate port connection and so i my duty name is interconnect one here and now i have used few coverage modules and after that i've used the clock generation recent generation and the uvm part so you can ignore all this part so we'll be seeing what are the parts relevant for coverage i will come back to this file once we uh once he had gone through the coverage module to write function coverage i have created a module called axain indf so this module is a generalized module which will define the call group for one set of ix interfaces that is the curve group for all the right address right data write response read address and read data channels now we will see here the arguments to this uh the ports to this modules are all the right interfaces which are xa right interfaces write address write data response and read address and data interfaces now we will see how to write cover points for this interfaces so this is interface definition for right address interface so it got an id which is really down to zero length and an address a length field and few other fields so we'll be focusing only on these fields which are interest for us so we we wanted to check whether some particular values are hit for these three fields in the interface so that we are defining a cover group which is called uh our address value so we will be writing uh the address based properties here so you can see that the right address and the read address has got this set of field which is id address and length and the write data and read data channels has got the fields id and data so these are specific to access protocol definition which i am not explaining here thus we are defining two set of cover points one for address bus and next for data bus so in the address bus call point we wanted to sample the id the address and the length and this is a call group definition for that so the group cover group name is addr bus file you can see that i am passing two arguments integer arguments which are low and high to define the bus the address range so um and next arguments which are the actual address and the id and the length so you can see that all these three arguments are passed as reference variable because i wanted to generalize this group and use this same group for multiple address and data channels write address and write data right address and read address channels thus these three arguments are passed as reference and the first cow point is for uh this bus which is uh 31 to zero and uh the protocol of axi is saying that uh every proto every signal here it is valid only if there is a violet and ready signal asserted the valid is asserted from the source and this is from the destination so this is protocol specific so the only if the valid and ready are asserted then all these fields are valid thus i am passing you can see that in the group i am passing the uh the bus the id uh the length and the valid and the ready fields are reference field so these are the reference fields uh which are the actual variables in the simulation which will be some actual variables once i assign to uh to some other variables and these are just values so these are asked by reference and these are passed by values so the first coupon definition is saying uh cover this particular bus whatever variable you are getting through this bus through through uh reference cover this variable uh if i don't leave these cover referred variable valid and radius asserted and these are the bins here where um the first violet law is between 0 to 500 here actually you can you make use of this law and if you wanted as you had learned in in the previous sessions now id val i just defined a curve point uh because it's a three down to zero um length a three down to zero length variable thus i'm covering all the way all the possible values of id and length uh just by simply writing a simplified point without any pins so these these three cow points are defined and again i'm defining another cross coverage which will cross all these three individual cow points so i wanted to make sure that i am getting every id and every combination of length with all these three different bins in the bus field now we will see the instantiation and we'll come back to the data part next so here you can see the cow group name is add bus file so it's it's declared like adidas file w added here and read it here and it is new like wddr is equally new 100 comma 500 so which is passed as the low and high variable and next variables you can see that these are the actual interface signal so write a ddr interface this is a signal this is interface which is coming through the port of this coverage module so this this is a name here write adder interface so this interface this in a input port interface dot w added here so which is the actual signal within this interface definition w hddr is passed as a reference variable for the bus value and similarly wad the add a w id a w length and a w violet and a w ready are passed as the reference uh reference arguments to this cover group thus these interface dot these signals will be sampled by the instance of this curve group named bus bus hdr bus file with an instance name of wrdr and in the same way you can see radr is again again instantiated for the read address channel so you can see that radio has created like read address interface dot addr id length while it and ready are used as the reference variables here thus this will be sampled now we will see the data data channel coverage definition for the database there is no length field thus we are only passing bus id and valid ready signals as reference and restore are same here and this cross is also defined for id and bus values and you say before the and for the response channel i am passing the response the id and violet ready signals as for response uh and this is the interface definition for this is a this is data channel definition and this is a write response channel definition so these are the only signals available in the response final now uh i've created instance for write that data bus values like w data and read data and for response i created one missions and knew it appropriately by passing the appropriate interface signals thus this particular module axi indf curve module will be creating coverage points for the signals which are passed to its interfaces to these interfaces what all are the signals we are creating uh cover point for this interfaces now we will see how to declare this inter this module and use with the actual simulation so in the test pin you have to create the instance of this axi ndf curve so here in the test bench after uh the duty instantiation i am creating the instance of x indf curve this is axi and df curve space axon df kaufman is module name i'm i'm connecting the right address interface to xa idd r1 interface and write address data and interface to axi write data one interface and so on thus i have created a cover point for all this interface one and in the same way you just need to create another instance for this axi ndf curve to enable coverage for the second interface so this is how you write generalized powerpoints now this line shows an example of binding a particular coverage module to an instance in the duty so this cow model fifo is defined in a different file uh with few ports and it is bind to a specific module that is instantiated within the duty so within the interconnect duty there is an instance of a module called axa right front and one and uh to that module i am binding this coverage instance however fun so this we had only seen in the previous sessions you can use the bind keyword if you wanted to connect your coverage definition to an inner module now we will run this simulation with this option text so the files will be downloaded once the simulation is over if you tick this option this test bench is using the uvm test uvm methodology and you will see a lot of um debug messages and finally you will see the result in receipt format file so this is a result and we will analyze result here once you unzip the result you will see a lot of files like this and you will see a file named curve.txt which is given in the do file and uh once you open this code.txt with some notepad plus plus editor you will be able to see the coverage report so here you can see it is coming the axi ndf cov1 is coming here with uh three this three cow group which are added bus value data bus value and uh response plus value and it is hit 23 percent and these two car points are hit zero percent uh it is because it is disabled in this relation the simulation is injecting only a few set of limited values uh to this address bus these reports will show only the group names and it will not show which bins are hit and which means are not hit and you will not be able to do the analysis but you can just make sure that your coverage your actual coverage definition is considered into the coverage database