Course: Systemverilog Foundations: L6.1 Transistor Level , Gate Level & Behavioral Modelling in SV

[00:00:01]transistor level gate level and behavioral modeling in systemverlog these are three types of modeling in systemvariog to implements any hardware using it in transistor level modeling you will specify the circuit as if it is connected only with transistors whereas in gate level modeling it describes the circuit only with logic gates in behavioral modeling it is described in a high-level abstract manner you will see an example for each of them here transistor level or switch level modeling now you are going to implement a nort gate in systemverlog here is the circuit diagram of a nor gate using pmos and nmos transistors here is the verilog program implementing a nor gate in transistor level modeling there are inbuilt functions in verilog that implements cmos transistors those are pmos and nmos now you will go through the program the name of the module is given as my underscore nor and it got two inputs a and b and an output y these are the internal variables used from the circuit diagram it is clear that it need a wire to connect the source of p1 to drain of p2 it is declared as wire c it also needs supply plus minus voltages which are declared with variables gnd and vdd now you need to instantiate 2pmos and nmos transistors using the inbuilt functions p motion and mohs named p1 p2 n1 and n2 the argument of those functions in order is the source drain and gate p1 source is connected to wire c drain to vdd and gate to input a in the same manner all other transistors are connected appropriately according to this circuit diagram this is an example of the transistor level modeling in verilog or systemverlog gate level modeling in gate level modeling the whole circuit is described using only logic gates similar to transes there are in-built functions in verilog that implements all seven logic gates now in order to implement your own nor gate using gate level modeling declare a module with input a and b and out y and connect those ports to an instantiation of the inbuilt function nor inside as shown here here is another example showing gate level modeling of 2x4 decoding with circuit diagram you can see that the inbuilt functions of and and not gates are used and connected according to circuit diagram behavioral modeling from the previous session it is clear that it practically impossible to implement a highly complex circuit in transistor level or gate level here you will use behavioral modeling which will describe the hardware similar to a programming language and the synthesizing tool will convert it to its equivalent gate level and transistor level circuits here is an example of representing a nor gate in behavioral modeling the statement assign y equals a bitwise or b is using the verilog bitwise or operator to generate the output here is another example of a multiplexer using verilog language constructs which you will learn in coming sessions here the implementation of a nor gate is shown in all three types of modeling together transistor level gate level and behavioral modeling you will always use behavioral modeling to describe any hardware in verilog or system verlog which is the whole purpose of using a hardware description language