Course: Systemverilog Design - 2 : L7.1 : Interfaces in RTL Design Coding

[00:00:01]interfaces a systemvrelog interface encapsulates the connectivity between different modules which may be design or testbench blocks and it bundles various input output ports of modules together in this session you will learn why you need to use an interface in your program and how to use before learning more about interfaces let's see why should someone use systemvrelog interfaces in the program here are the signals in an ax i write address channel bus if you are not familiar with axi protocol just understand that it is a master slave protocol and in this channel the master will drive all these signals along with this valid and the slave will drive the ready signal assume that in your design you have four different sub-modules which are processing data in this channel in conventional port-based module modeling you need to list down all these signals in all four modules and specify their directions as input or output based on the functionality of the module thus you will write a lot of redundant code which is difficult to maintain and comes with more probability of introducing bugs in the design the same problem will be encountered if the top level design module has also this bus as ports and then you need to connected the signals and drive them from the test bench also systemverlog provides a new language construct called interface to deal with this problem an interface is used to bundle a group of wires or signals and to manage their connectivity synchronization and optionally the functionality of the communication between two or more blocks this is an example of defining a simple interface interface definition should be within the keywords interface and end interface the syntax is the keyword interface name of the interface and arguments here the argument is only the clock signal within the interface request and grant are two variable that are bundled in the interface note that they are of type logic this is how you use the interface within a module instead of listing individual signals in the port list of the module the interface name given here simple underscore interface is the name of the interface that you have given while it is defined and intf is its instance within the module named design not you can access the individual signals in the interface like intf.clk intf.request etc to pass an interface into a module you need to create an instance of the interface somewhere above the hierarchy of the module and pass that interface instance while instantiating the module here the design module is instantiated within the testbench module before that the interface named simple underscore interface is instantiated with name tb underscore intf and it is passed as the argument in the design module instantiation now once you drive signals in the tb underscore intf as shown here those will be driven into the design instance named d1 while instantiating an interface you need to pass all the arguments in the interface typically only clock and reset signals will be listed as arguments in any interface definition and all other signals will be declared as internal signals of type logic this usage will be trivial when you learn mod ports in the next session