Course : Systemverilog Assertions : L11.2 : Cycle delay operator

[00:00:01]sequence expressions so as you have seen in the previous lecture this is a syntax of defining a sequence so as i said earlier the whole intelligence is defining sequence expressions so now we'll learn how to define sequence expression to match your requirement these sequence expressions are again composed with the boolean expressions and this time you could add either cycle delay operators or repetition operators or both of them in the sequence expression to specify repetition or cycles of operation so you will learn more about this in the coming session but the sequence expression is effectively multiple boolean expressions separated by these two operators either cycle daily operators and repetition operators now the cycle delay operator the cycle delay operator specifies the delay from the current clock cycle to the next element in the sequence and it is specified using two higher symbols followed by a number so in the sequence expression you will give the first expression followed by a hash hashen and the next next expression and the second expression should come after n clock cycle from the end of the first first expression so this n can be any any individual number including 0 now here is an example i have defined a sequence uh which clocking given as positive edge of clock and the first expression is a valid and the second expression is ready and it is separated by a cycle delay operator which is hash hash fund so it means after while it being true the next expression which is ready should be true after one clock cycle from this point so this is the waveform diagram so once while it is true so at this clock while it will be evaluated as true and next clock cycle the radius should be evaluated as high at this point so instead of one if you are giving two like valid hashes to ready it will be like after while it going high after exactly two clock cycles one and two the ready should be evaluated as too now you will learn more about the cycle delay operators you can specify different kind of delays using the cycle delay operator so a fixed delay and zero delay can be specified and they can be can multiple boolean expressions can be concatenated concatenated as well so now we are defining more and more complex properties if you go through the previous example here we are just make asserting that after a violet is being high the next clock ready should be high now if you wanted to specify a sequence which is exactly looking that like this waveform so the wireless should be high for a single clock cycle and after that uh the violet should be de-asserted and and the next clock cycle ready should be asserted only for a single clock cycle so it is written by using this statement so it is specifying that while it is going true at this point and in the next clock after one clock while it is going uh uh false or it is evaluated as zero so it is satisfied here so it is measured as one here and it is measured as zero at this point valid and if you see the next delay operator it is specified as hash has zero so it is as i said earlier you can even specify a zero delay as a cycle daily operator and if you give it a zero it means the current close cycle so this evaluation is reached at this point and and exact same clock cycle the ready should be asserted so at this exact point in the same clock cycle ready should be measured as high so you are specifying this is high and after this one clock period uh the ready should be ds added so it's saying not ready so at this point ready should be zero thus by using the sequence you have specified that the violet signal should be asserted if the violet signal should be is high on a particular close cycle the next it should be high only for a single clock cycle and the very next clock cycle the radius should be high for a single clock cycle as well so this how this was using fixer delays and it is also possible to use a range of delays so this is a syntax you use a range of delays instead of giving a fixed number after hasher in in a square bracket you could give a range like zero column to specifies a range of zero to two it implies that the next statement uh could be true in any of this range so it could be like uh it it could be true after zero clock or one o'clock or two o'clock so this is this property will be true for all these uh combinations so here while it is going high and decided after that and in the next clock cycle if while ready is going high ready could go high either in zero or one or two clock cycle after the violet is detected as low so this is how you specify a range of delays in sequences unity cycle delay so you don't need to necessarily specify the first expression for a cycle delay if you are not specifying the first expression here the default first expression will always be true so for say for example if you're just simply specifying like a sequence like hash h3 ready it is equivalent to specifying one hash one heart so this one bit one is nothing but a true condition so uh it you are simply specifying from an evaluation point after three clock cycles the ready should be asserted so this will be useful when you use different sequence operators like and or intersect etc also you could specify the range delay range as unbounded so here is an example say uh if if i giving the second argument in the range as a dollar symbol it specifies an unbounded delay so that means after while it is going going high from one to infinite number of clock cycle the ready should be high so the infinite means any clock cycle before the simulation is getting ended so this is by using a dollar symbol in the range operator you could specify an unbound delay as well thus in this lecture you have learned how to specify different types of delays either a constant delay or a range of delay or a unary delay or unbounded range of delay