Course: Systemverilog Foundations: L5.5 : Arrays & Operators in Systemverilog

[00:00:00]arrays in verilog and systemverlog a variable is defined as a fixed size array by adding the size of the array in square brackets while declaring it since verilog is used to model hardware the arrays are used to define a bus signal in the hardware and therefore array index l be specified from msb to lsb or lsb to msb an example is here bit a 7 down to 0 will define the variable a as an array of width 8. if the array is not used to define a bus you can use the size directly instead of the index like bit a of 8. you can also define multi-dimensional arrays by specifying multiple dimensions while declaring it fixed-sized arrays can be declared in two different types packed or unpacked if the array size is given on the right-hand side of the variable it is an unpacked array if it is on the left-hand side it is packed array thus here the variable a is an unpacked array of bits and here it is packed array the difference between those is in memory allocation in case of a packed array an 8-bit array will be assigned with eight packet bits that is it is guaranteed that the variable is assigned with eight continuous location in the memory but in case of unpacked arrays it may or may not be allocated continuously let's look at an example here the variable a is a two-dimensional array which is defined as packed it need four multiplied by eight equals 32 locations and those will be allocated continuously in the memory as shown here this is your array of zero this is a ray of one and so on this will be array of one of six if you define it as a two-dimensional unpacked array its memory location will be somewhere in the memory and need not be continuous you can mix an array as packed and unpacked here the array is of three elements which is unpacked and each element in the array is of eight bits which is packed so it will be allocated in the memory something like this apart from fixed-sized arrays systemvrelog supports dynamic arrays associative arrays and cues as well those will be only used in the testbench code and they are not discussed here operators these are the operators available in verilog and system verlog arithmetic logical relational conditional bitwise and reduction operators are listed here they are not described in detail as most of them are self-explaining except few if you look here there are two types of equality checks available the first equality and inequality checks are similar to other programming language like c with two equals sign but these are specific to verilog and systemverlog the difference is that the second one will take care of x and z while comparing that is when three equals are used it will return true only when all bits of the variable are exactly matching including the x and z values another operator that is used quite commonly is the conditional operator it is similar to the conditional operator in c e if will return the first value if the condition is true and second one if it is false in this example if both a and b are equal one will be returned by the conditional operator and assigned to the variable result else 0. cascading of conditional operator is also allowed