Course : Systemverilog Verification 4 : L9.4 : Random TB Example : Writing Sequencer & Generator

[00:00:01]in this session we are using all the components that have developed in the previous example and only the generator class will be modified so i have written a new generator class in a new file generator underscore sequence reduced ph and that is included instead of the generator svg in the main program so we will look at the generator.svg file so class name is same as command generator so there is no need to change any other env components the only change is in the run task if you see the previous run task in the previous generator it was just listing out the command generation one by one and calling in a loop so in the new command generator sequence instead of listing out them one by one i have used the run sequence uh system value keyword to generate a random transaction sequence so here the random sequence is again called in a loop so this run sequence will be called 10 times and every time this run sequence is executed a different type of sequence will be randomly generated so look at the run sequence statement here the production name is all under cmd and again the production all command is calling or choosing any of the three productions it's either a cpa command production or a memory command protection or or it will first call the cpu command and memory command so the cpa command production will choose one of the cpu command and memory command production will choose one of the memory command productions finally in every in individual productions i am calling a task to generate that particular transaction so if you see the production name nope it's calling a task called g underscore nope so this task implementation is again here in the same class the task underscore nope uh there is a lock declaration of the cpu know and the note is created assert randomized and it is put into the mailbox the same way all the other tasks g underscore are general sub and g n squared it will uh produce respective commands print them and put into the mailbox so again coming back to the run sequence you can increase the complexity of a random choice by adding more productions here say for example in the cpu command protection i have listed a choice between nope add sub uh which are the productions uh which is nd here or it's a choice between no point art and an art followed by a sub again you can add one more protection saying sub followed by no and all the combinations you can put or it can be a combination of uh choosing all three commands in the same way the production mem command is a choice between either a single command or all the four commands in the in this order like mem waits to load store and copy or you can put any random combination in a random combination of three or two or you can even change the order of this in the last production so everything will result in different uh sequence generation every time the run sequence is called if we compare this com new command generated with the previous one you can see that in the previous one it was all this command sequence was in a predefined order all the time when this loop is executed first a new op is execute generated next year rd is generated next a load register is generated and next a copy is generated so it's in a predefined manner but in the new one when you use the run sequence you are able to produce a random sequence of transaction by simple system reload code this run sequence is creating random scenarios to your test bench now when i run this code and see the simulation log file so you can see that the final output there is no predefined order first remember it is generated then scp knob cpu then mem load mem weight again another memo load so there is no connection between these transactions when when we are comparing the previous simulation it was always in a predefined order which we have listed in the generated but here the order of the transaction itself is getting randomized and we were able to produce random sequence of transactions