Course: Systemverilog Foundations: L12.1: Simulation Example: Adder

[00:00:01]in this session you will go through few simple systemvrelog programs that implements some basic circuit in the design and their testbench codes first program is implementing a simple adder circuit here is the design program the module name is adder which got inputs a b c and sum and c out we have already explained the program in the initial session that introduced the idea of using module in systemvr log here is the test bench for the adder tb module name is test underscore bench here three internal signals are declared as logic 7 down to 0 which of with 8 with names a b and s next two single bit variables are declared as logic c in and c out next you will instantiate the design module which is adder the instance name is adder 1. in the ports of the module sum c underscore in and c underscore out are connected explicitly to internal signals s c in and c out rest of the ports which are a and b will get connected implicitly to the internal variables a and b using dot star this is the code to add signal values to database so that they can be viewed in the waveform next is the functional part of the test bench in an initial begin end block the variables a b and c and are assigned with different set of values before changing the values of them a single unit time delay is called using the hash1 statement so that the changes are visible in the waveform finally the dollar finish function is called after the fifth set of values now let's run the simulation and see the waveforms here is the waveform you can add variable using the get signal button and remove them using the x button you can see that it was simulated for 6 nanoseconds remember the time unit was set as 1 nanosecond initially all signals are the unknown value x when the variable takes x values the bus signals will show x in the waveforms and single with single will get the red color after one unit time delay you assigned values 1 2 and 1 to a b and c in thus sum will be 4 and c out will be 0.

[00:02:48]in a similar manner the variables are changing after every nanoseconds remember that the radix shown is in hexadecimal thus one o will be value 16 in decimal finally when a is ff and b is 1 the sum will overflow its 8 bits and c out will be set to high now you will make an intentional mistake in the program let's say you forgot to assign any initial value to the carry in signal c in i am commenting out this line and running the simulation again you can see that even though the input a and b are getting changed after every time unit the output is x the reason is the c in signal is uninitialized and takes the value x when an x is added to the sum it will also propagate x and the output will also be x you must be careful to initialize signals appropriately even if you are not changing their values within the program this finished the program you have written the design and tb modules simulated and verified the design interactively