Course: Systemverilog Design - 1 : L4.1 :Verilog Always Block

[00:00:01]verilog always block in this session you will learn more about the usage of always block specific to verilog hdl even if you write the always block in a wrong way to model a specific circuit the compiler will not flag any errors but the final circuit generated in the ic will not be the one that you intended therefore it is very important to understand how to write the always block in the right manner for a designer this session will first teach you about the always block and verilog different types of circuits produced using it and problems in verilog with its usage then in the next session you will learn about the systemvr log extensions to verilog always and see how they will help in solving the issues with verilog always block the verilog always procedural block is an infinite loop that repeatedly executes the statements within the loop in order for simulation time to advance the loop must contain some type of time control or event control this can be in the form of a fixed delay represented with the hash token a delay until an expression evaluates as true represented with the weight keyword or a delay until an expression changes value represented with the at token in general you will use it with a sensitivity list in the beginning of the statement along with the at the rate symbol its general syntax is always at the rate sensitivity list within brackets begin multiple statements end whenever any variable in the sensitivity list changes the block will be executed the statements within the block will be executed sequentially the verilog always procedural block is a general purpose keyword which can be used for modeling any type of circuit in a design or rtl code the always procedural block can be used to model combinational logic latched logic and sequential logic the same general purpose always procedural block is also used in test benches to model different verification tasks this causes an a substantial burden on software tools for synthesis and formal verification the reason is during synthesis in order to identify the type of circuit implemented in the always block the tool need to go through the code and analyze it because the same always keyword can be used to implement different types of circuit like sequential and combinational thus with the general purpose application of the always procedural block the design intent will not be clear for the synthesis tool this can happen the other way around that is a designer can write wrong type of code in an always block to generate a specific type of circuit as well there are the issues with the usage of the general purpose always block and systemvrelog avoids this ambiguity by adding extra type of always block for different type of circuits which you learn in the next session before going into systemvr log extension of always block here are the guidelines for using the always block in order to generate different type of circuits in the ic these will useful if you are coding in verilog or not allowed to use systemvrelog specific always types there are many rules for the correct usage of always block for synthesis out of which few are listed here if you are allowed to use system prologue specific keywords there you may ignore these and go to next session to represent combinational logic with a general purpose always procedural block the always keyword must be followed by an edge sensitive event control which is the a token the sensitivity list of the event control cannot contain a posedge or negej qualifier the procedural block cannot contain any other event controls also all variables written by the procedural block must be updated for all possible input conditions to represent a latched logic the same set of above rules should apply except one here at least one variable written to by the procedural block must not be updated for some input conditions to represent sequential logic with a general purpose always procedural block the always keyword must be followed by an edge-sensitive event control after the a token in the sensitivity list you should use either possege or negege qualifier along with a clock signal the procedural block cannot contain any other event controls also any variables written by the procedural block cannot be written by any other procedural block these guidelines are needed because a compiler cannot enforce them as verilog always procedural blocks are general purpose procedural blocks which are used in the test bench code as well