Apple M1 Chip Deep-Dive

本站添加: 2026-05-30

[00:00:00]Apple has always been defined by product  design. A symbiosis of form and function, creating instantly recognizable shapes. There’s  no question, you just know if it’s Apple.

[00:00:13]But something is changing, another type of design  is starting to leave its mark. Apple isn’t just a product design company anymore. With the launch  of the A4 back in 2010, Apple made its first steps as a chip design company. In my opinion the most  important decision in the entire company history.

[00:00:34]Today, what’s inside an Apple product  is as important as how it looks and feels on the outside. Apple Silicon  isn’t just a marketing term anymore, it’s a success story. But unlike product  design, the beauty of chip design stays hidden, deep inside your iPhone or Mac. You can’t see it. Something we will change with this video.

[00:00:57]Let me take you on a journey into the incredible  beauty of Apple Silicon, brought to life by ultra-high resolution die shots from none other  than Fritzchens Fritz. And what better way to start than with the legendary chip that defined  Apple Silicon as we know it today: the Apple M1.

[00:01:18]The high-resolution die shots in this video are actual photographs, taken from an M1 MacBook Air. First, the logic board was removed from the chassis, the M1 package was de-soldered and the metal heat spreader removed. The M1 uses so called on-package memory, with two LPDDR4x DRAM modules right next to the chip, on the same package. On-package memory reduces the distance data has to travel from the chip to the memory and back, increasing efficiency. It also allows for an overall smaller and more space efficient design.

[00:01:52]Next, the silicon die was removed from the packaging substrate. As an interesting observation, the M1 employs so called “embedded silicon capacitors”, the tiny rectangular shapes you can see in this image. They help with power delivery to the most crucial parts of the silicon.

[00:02:09]Finally, the entire silicon die was ground down, layer by layer, until the transistor structures became visible. Revealing the true beauty and complexity of the chip.

[00:02:26]The M1 was produced in TSMCs N5 process node and contains approximately 16 billion transistors on a 120.4 square millimeter die. If we include the scribe lines, which are the border areas that remain after the wafer dicing process, the total size increases to 123.14 square millimeters.

[00:02:47]As a System-on-a-Chip, or SoC, the M1 combines all system functions inside a single chip.

[00:02:54]From Apple’s own documentation we know that the M1 contains an 8-core CPU, divided into four performance and four efficiency cores, an 8-core GPU, a 16-core NPU, a System Level Cache, a 128-bit memory interface, plenty of IO including Thunderbolt and complex Media- and Display Engines plus Digital and Image Signal Processors. Seeing a high-resolution die shot for the first time always comes with a combination of feelings. Mostly awe and confusion. Even as an experienced chip analyst, it takes some time to take everything in. Remember, we are looking at a picture painted by 16 billion transistors. And even in an ultra-high-resolution die shot like from Fritzchens Fritz, a single pixel contains thousands of transistors. If we want to label as many areas as possible, we need a strategy. I always like to start at the shorelines of a chip, because that’s where you place everything that has to communicate with the outside. Which means the memory interface and all the IO components. Always a good start. But keep in mind, any chip analysis includes some kind of uncertainty. I’ll mention when we cover areas that I’m not sure about. The memory interface of the M1 is visible on the upper left, top and right shorelines of the chip. We can count a total of eight 16-bit memory PHYs, for a combined 128-bit wide memory interface. Apple’s memory architecture is very space efficient, tightly integrating memory control functions and PHYs. The PHY, or physical layer, provides the literal contact points for the interconnects that run all the way to the on-package DRAM we saw earlier. Staying on the shorelines, but switching to the bottom part of the M1, we can spot a single Display Port PHY in the very left corner, right next to the Thunderbolt logic. The two Thunderbolt 3 ports are divided into two control areas and two PHYs. If we look closer, we can see that the control area also includes a standard USB logic block, which adds the USB4 functionality to the Thunderbolt ports.

[00:04:57]Following along the edge of the chip, the PCI-Express area is next. It offers a total of five physical lanes, with the controller above the PHYs. PCI-Express is used to connect the WiFi and Bluetooth module, handles ethernet on supported products like the M1 Mac mini or the M1 iMac, and for passthrough support. If we look closely, we can see that the physical implementation of Thunderbolt and PCI-Express PHYs are the same. That’s because both use high-speed SerDes, that translate the IO signals from parallel to serial and back again. SerDes is short for Serial-Deserial and Apple uses the same SerDes design for both PCI-Express and Thunderbolt.

[00:05:37]To the right of the PCI-Express area is a single, small USB PHY, followed by a much larger area. I’ve seen this labeled as a lot of things, but what we are looking at primarily is Apple’s proprietary NAND Storage Controller or ANS for short.

[00:05:53]Unlike other companies, Apple uses a very unique approach when it comes to NAND storage devices, aka the SSDs. The actual physical SSD only contains the raw NAND chips, because the storage controller is located on the SoC itself. It contains about 3.5 megabytes of fast SRAM to buffer and sort incoming data streams and an eFuse that holds the storage encryption keys.

[00:06:17]The on-the-fly encryption also requires a dedicated AES engine. That’s why, according to Apple documentation, the ANS is closely connected with the on-board secure logic.

[00:06:27]Right below the ANS controller we can spot another oddity. Apple doesn’t use PCI-Express to connect their SSDs with the SoC. Instead, Apple is using a parallel dual-channel NAND fabric with a total of 92 visible IO pads. The M1 connects to the SSD without using SerDes, it’s a direct parallel storage access. One of the reason Apple’s SSDs are so blazing fast, if they actually use enough NAND chips to saturate the dual-channel interface. If we overlay the top metal layers over the transistor layer, you can actually see that the PHYs are connected to a large number of interconnect pads. The NAND fabric is especially interesting to look at, because the tightly clustered contact pads are spread out over a much larger area on the top metal layers.

[00:07:14]But the weird stuff isn’t over yet. The large PHY cluster next to the NAND controller is something really special. And really weird. It’s Apple’s proprietary camera interface. If you are thinking webcam now, you are wrong. It’s not for a webcam, it’s for a large, high-resolution camera cluster.

[00:07:32]Like on an iPhone. Or an iPad. And the M1 iPad Pro is actually the only product with an M1 chip that uses this pretty large PHY. On all other M1 based products, no matter if MacBook Air, MacBook Pro, the Mac mini or the iMac, this area isn’t functional. Apple implemented this PHY for a single product only. Talk about dedication. The webcam on a MacBook or iMac is connected via a tiny MIPI D-PHY in the top right corner of the chip. This PHY also reads the IR camera that enables FaceID and on the M1 iPad Pro. This concludes our journey around the shorelines of the M1. Edge space is limited, that’s why it’s one of the most valuable areas of a die.

[00:08:15]The M1 doesn’t have a massive amount of IO, yet it still uses a majority of the available shoreline.

[00:08:21]Next, let’s take a look at what’s inside the chip. The big IP blocks. I’m talking CPU, GPU, NPU.

[00:08:29]With about 23.26 square millimeters, the GPU block covers the largest area on the M1. We can spot a total of eight GPU cores in the upper left to center area of the die, connected by shared control logic. A single GPU core takes up about 2.48 square millimeters. On some binned M1 parts, one of the eight GPU cores is deactivated. This might be done via a small cluster of eFuses on the very left of the GPU. I’ve seen attempts to further dissect the individual GPU cores, but without input from Apple it’s mainly a guessing game.

[00:09:04]Once this video is live, Fritzchens Fritz will publish the full high-res die shots, so everyone is more than welcome to try and analyze the GPU cores in more detail.

[00:09:12]Right below the GPU, we can spot the so-called System Level Cache. The SLC acts as a kind of last-level cache for basically the entire system, which means CPU, GPU, NPU and other areas can use it alike. The SLC is also a central hub for the data fabric that connects the entire chip. On the M1, the SLC contains a total of eight megabytes of SRAM, split up into four sections with two megabytes each. By the way, one megabyte of SRAM takes up approximately 0.28 square millimeters and is comparable in size across all major IP blocks.

[00:09:47]Next, the large CPU P-core cluster sits to the left of the SLC. It comes with four Firestorm performance cores, two on top and two below the shared level 2 cache in the center.

[00:09:58]A single Firestorm P-core is about 2.25 square millimeters in size.

[00:10:03]On paper, the CPU cores in the Apple M1 are based on an ARMv8 architecture, but that’s only half the story. Apple has long developed its own in-house ISA extensions and Apple Silicon is more and more transitioning toward a unique version of the underlaying ARM RISC architecture.

[00:10:20]The shared P-core level 2 cache has a total of twelve megabytes, that’s more than the SLC.

[00:10:26]The P-core cluster also comes with a dedicated AMX unit, which is an Apple specific matrix accelerator. Think AI calculations. With a total of 15.42 square millimeters, the Firestorm P-core cluster is only second behind the GPU. And quite a bit larger than the E-cores.

[00:10:44]The E-core cluster also comes with four CPU cores, but the Icestorm E-cores are actually tiny with only 0.6 square millimeters per core. All four Icestorm cores have access to a four-megabyte large shared L2 cache and the E-core cluster also comes with its own AMX unit. With a combined size of 5.3 square millimeters, the size difference between E-core and P-core cluster is almost 3x.

[00:11:11]Last, but not least, we have the Apple Neural Engine, also called ANE or more commonly, NPU.

[00:11:17]It’s nestled right in-between the P- and E-cores and very recognizable due to its striking layou On the M1, all 16 cores are easily visible and they surround the shared scratchpad RAM. A single NPU core is truly tiny with only 0.21 square millimeters.

[00:11:35]With that, we have labeled all the major function blocks of the M1. The memory system sits on the edges of the chip and the bottom shoreline is mostly used for IO PHYs.

[00:11:45]The four major function blocks, GPU, P-cores, E-cores and NPU are tightly clustered around the central System Level Cache. In my opinion a very skillful and pleasing SoC layout.

[00:11:57]But there is still a lot of unmarked area left. What are those?

[00:12:02]The unmarked areas contain a lot of different essential function. For example, the Display Composition Engines that drive the display outputs. The M1 also contains a robust Media Engine with dedicated De- and Encode Engines, but unlike the M1 Pro and Max, no Pro-Res support. And then there is an Image and a Digital Signal Processor, a general IO Root Hub and lots of data path logic. I’ve seen plenty attempts to label individual areas and they all make strong points. In my opinion it’s very likely that the large mirrored cluster, which borders the GPU in the top right, contains the Display Composition Engines. That’s also the general area where audio processing happens, but it’s hard to label individual blocks.

[00:12:42]A bit further down we can find what most likely is the Image Signal Processor and the area close to the bottom PHYs is where the video codec and related areas are located.

[00:12:52]But all of those areas are based on more or less educated guessing. I’ve seen other people come to different conclusions and they often make a compelling argument.

[00:13:01]The best we can do, if we want to stick to what we know, it to outline notable and repeating patterns. Comparing the M1 to die shots of the M1 Pro and Max could also help clearing up specific function blocks. And if you want to get super technical and start a competitive analysis, looking at a live heat map of the chip while testing specific functions could give valuable insights in what is what. There’s no doubt, the Apple M1 was a revolution. Not only did it show that Apple could design a laptop class chip, it actually outperformed the competition in both performance and efficiency. With the M1, Apple Silicon became the gold standard. And with it, Apple’s image expanded. From just a product design company, to a chip design power house. The following M-series generations only improved on that image and today even normal consumers talk about Apple Silicon like they talk about the design of a new iPhone. Apple Silicon has become a brand in of itself and part of Apple. Something that’s reflected in the choice of the upcoming CEO.

[00:14:05]This video is only the first in a planned series of Apple Silicon chip deep-dives. The chips are already in our hands, but the creating such beautiful die shots is a work of art, and art takes time. Even if the artist is as talented as Fritzchens Fritz.

[00:14:20]I would like to know if some of you have used or are still using an M1. If you do, leave a comment down below.

[00:14:26]I hope you enjoyed this video and see you in the next one!