Course: Systemverilog Foundations: L12.2 : Simulation Example: Multiplexer

[00:00:01]next you will go through design and test bench code of an 8-input multiplexer here is the program assume that the width of each data is one byte the name of the module is multiplexer and its ports are inputs data cell and output y note that data is an unpacker array of size 8 and each element in the array is a packet data of width 7 down to 0.

[00:00:26]with this you can easily access 8 individual bytes in the program in the functional part of the program an always block is used with sensitivity list as cell port thus whenever the cell input changes this block will be executed in the always block a case statement is used with the select line cell when it is ooo the output y is assigned to data of 0.

[00:00:53]when it is 001 output is data of 1 and so on finally in the default block an error is flagged using dollar display function available in verilog and systemverlog it is a function that formats its string arguments and prints to the simulation log the dollar display function is very much similar to the print function in c language remember that this function is not synthesizable but you can add them in your design file to flag errors or illegal scenarios next you will go through the test bench code first is internal signal declaration and next is the instantiation of the design module the port data is connected to d in cell is connected to select and y to y even though the design is combinational circuit which doesn't need a clock signal it is generated in tb here so that the inputs can be changed based on the clock here is the functional part of the tb in an initial block first the dn elements are assigned with some fixed values here next in a for loop the code is waiting for the next positive edge clock and changing the value of select signal from 0 to 8.

[00:02:18]finally dollar finish is called to end up the simulation here in an always block whenever the value of y is changing the values of select and output y is printed into the simulation log now we will run the simulation before looking into the waveform let's if check the debug messages were printed into simulation logs here are those messages saying the output changes when the select line is changing here is the waveform this was simulated from 0 to 900 nanoseconds that up to nine clocks initially all signals are x when the select line changes the output is changing to different data inputs this finishes the program simulation