Logic Gates using VHDL

[00:00:00]Hello, everyone. Welcome to Neso Academy.

[00:00:04]In the previous lecture, we implemented our first VHDL code in Vivado.

[00:00:10]Where we learned how to create source files, how to write the VHDL code in Vivado code editor, how to generate the RTL schematic, and how to analyze the simulation waveforms.

[00:00:26]And today, we are going to understand how to implement all seven logic gates in Vivado.

[00:00:35]Now, logic gates are the building blocks of the digital systems.

[00:00:40]Now, why we are calling these building blocks logic gates as logic gates?

[00:00:47]Because they act like a real physical gate.

[00:00:52]Just like a physical gate allows or blocks people, a logic gate allows or blocks the flow of data based on the mathematical logic.

[00:01:05]Meaning, a logic gate makes logical decision to generate the output based on the mathematical logic of the input combination.

[00:01:16]For example, an AND gate decides to generate the output if input A and input B both are active.

[00:01:27]So, what are logic gates?

[00:01:30]Logic gates allow or block the flow of data based on the mathematical logic.

[00:01:37]And I hope you understand this. So, in this lecture, we will implement all seven logic gates using VHDL with the help of data flow modeling.

[00:01:49]Why data flow modeling?

[00:01:52]Because logic gates are based on Boolean equations. And we have already studied that data flow modeling is the most suitable choice for the Boolean expression.

[00:02:04]Now, let's understand all seven logic gates one by one.

[00:02:09]Starting with the first basic logic gate, the AND gate.

[00:02:14]Logic gates are categorized into basic logic gates, universal logic gates, and derived logic gates.

[00:02:23]Now, basic logic gates include AND gate, OR gate, NOT gate.

[00:02:29]Now, why we are calling them as basic logic gates?

[00:02:33]Because they are the fundamental building blocks for all digital circuits.

[00:02:38]We can create any complex circuit by using these basic logic gates combination.

[00:02:44]Where AND gate represents logical multiplication, OR gate represents logical addition, NOT gate represents logical inversion.

[00:02:56]Now, let's get back to the AND gate.

[00:03:00]AND gate returns one when all inputs are one.

[00:03:04]So, in case of AND gate, output will be one when all inputs are one.

[00:03:12]Let's understand this using the two input AND gate's truth table.

[00:03:18]So, this is the truth table of two input AND gate. Here we have two inputs, A and B, and one output, Y.

[00:03:27]For two inputs, we will have four input combinations, 00, 01, 10, 11.

[00:03:35]Now, let's see the output for the first input combination.

[00:03:39]Here output Y is equal to zero when both inputs, A and B, are zero because AND gate returns one when all inputs are one. And here both inputs are zero.

[00:03:54]Therefore, the output is zero.

[00:03:57]Now look at the second input combination. Now here A is zero and B is one.

[00:04:03]In this case, output Y is zero. Because here we can see input A is zero.

[00:04:10]Now in the third input combination, when A is one and B is zero, output will be zero.

[00:04:18]Now look at the last and the fourth input combination, when both inputs A and B are one. Now in this case, output is one. Because here we can clearly see output is one when all inputs and here when both inputs are one.

[00:04:36]So, I hope you understand this truth table.

[00:04:40]Now the reason why we are calling this gate as an AND gate is because it acts like the English word and.

[00:04:51]Here, output requires input A and input B both to be one in order to generate the output as one.

[00:05:04]Therefore, we are calling this gate as the AND gate.

[00:05:08]And I hope you understand this. Now let's see the symbol for the two input AND gate.

[00:05:14]Now this is the symbol of the two input AND gate, which looks like a letter D.

[00:05:19]Here we have two inputs, A and B, and output Y.

[00:05:25]And I hope you understand what is the AND gate. Now let's see the second basic logic gate, OR gate.

[00:05:34]OR gate returns one when at least one input is one.

[00:05:40]So, in an OR gate, the output is one when any single input is active or one. Now, let's understand this using the two input OR gates truth table.

[00:05:54]Here we can see we have four input combinations. Now, look at the first input combination.

[00:06:00]When both inputs A and B are equal to zero, that's why the output Y is zero because as per the definition of the OR gate, output will be one when at least one input is one. And here in the first input combination, both inputs are zero.

[00:06:21]Therefore, the output is zero.

[00:06:23]Now, look at the second input combination.

[00:06:26]A is zero, B is one.

[00:06:29]Now, here B is one. Therefore, the output is one.

[00:06:33]In the third input combination, A is one, B is zero. Now, here A is one.

[00:06:40]Therefore, the output is one.

[00:06:43]In the last input combination, both inputs are one. So, output is one.

[00:06:50]And I hope you understand why we are calling this gate as the OR gate because it acts like the inclusive English word or in which output becomes one if input A or input B or both of them are one or active.

[00:07:14]So, I hope you understand why we are calling this gate as the OR gate. Now, let's see the symbol for the OR gate.

[00:07:23]Now, this is the symbol for the two input OR gate.

[00:07:27]On the input side, it has a curved shape or a concave shape, which represents a funnel which takes multiple input combinations and generate a single output.

[00:07:40]So, we are done with the OR gate. Now, let's understand the third basic logic gate.

[00:07:47]NOT gate.

[00:07:49]NOT gate returns the opposite value of the input. So, the output is the NOT of the input.

[00:07:58]So, zero becomes one and one becomes zero.

[00:08:03]In the truth table, when input is zero, output will be one and when input is one, output will be zero. So, NOT gate returns the opposite value of the input.

[00:08:16]Now, let's see the symbol of the NOT gate.

[00:08:19]It includes a triangle pointing to the right with a bubble at the end.

[00:08:24]Now, what happens if we remove this bubble?

[00:08:28]We are left with this triangle.

[00:08:31]And this triangle represents a buffer.

[00:08:33]Now, what is a buffer?

[00:08:35]Buffer is a circuit which passes the same signal as it is.

[00:08:39]So, in buffer, this input A will reflect as it is at the output Y.

[00:08:46]So, by adding this bubble, we are inverting the input.

[00:08:50]So, this bubble is performing the inversion operation of the input.

[00:08:55]So, I hope you understand all three basic logic gates. Now, let's see the universal gates. Universal gates include NAND gate and NOR gate.

[00:09:08]And why we are calling them as universal gates?

[00:09:12]Because by using either NAND gates or NOR gates, we can implement any other logic gates or any other digital circuit in the universe. Therefore, we are calling them as universal gates.

[00:09:27]Now, let's see the NAND gate.

[00:09:30]Now, here the word NAND means NOT plus AND. So, NAND gate is the inverse of the AND gate. Therefore, it returns zero only when all inputs are one.

[00:09:45]So, in NAND gate, output will be zero when all inputs are one.

[00:09:51]Let's understand this using the truth table.

[00:09:54]Here we have four input combinations.

[00:09:57]And for four input combinations, the outputs are 1 1 1 0.

[00:10:03]In the case of the AND gate, the outputs were 0 0 0 1.

[00:10:11]So, NAND gate is the inverse of the AND gate.

[00:10:16]In the truth table, we can see NAND gate returns zero when all inputs are one.

[00:10:22]So, I hope you understand why NAND gate is the inverse of the AND gate. Now, let's see the symbol of the NAND gate.

[00:10:30]NAND gate is the AND gate with inverted output. Here bubble represents the inversion of the AND gate.

[00:10:39]So, we are done with the NAND gate. Now, let's see the second universal gate, NOR gate.

[00:10:47]Now, the keyword NOR means not plus or. So, NOR gate is the inversion of the OR gate.

[00:10:57]Therefore, NOR gate returns one only when all inputs are zero.

[00:11:04]When all inputs are zero, then in the case of NOR gate, the output will be one.

[00:11:11]Now, let's see the truth table.

[00:11:13]Here we have four input combinations.

[00:11:16]Now, look at the first input combination, when A is zero and B is zero. So, here both inputs are zero.

[00:11:23]That's why the output is one. And as per the definition of the NOR gate, NOR gate returns one when all inputs are zero.

[00:11:32]And for other input combinations, outputs are zero.

[00:11:36]So, here outputs are 1 0 0 0.

[00:11:42]And in the case of the OR gate, the outputs were 0 1 1 1.

[00:11:50]So, NOR gate is the inverse of the OR gate. Now, let's see the symbol for the NOR gate.

[00:11:57]So, NOR gate is the OR gate with the inverted output. Now, here the bubble represents the inversion of the OR gate.

[00:12:07]So, I hope you understand the universal gates. Now, let's see the third category of the logic gates, derived gates.

[00:12:16]Derived gates include XOR gate and XNOR gate.

[00:12:21]Now, why we are calling them as derived gates?

[00:12:25]Because they are derived using the basic logic gates, AND gate, OR gate, NOT gate.

[00:12:32]Now, let's see the first derived logic gate, XOR gate.

[00:12:37]XOR gate returns one when the inputs are different. So, in XOR gate, output will be one when all inputs are different.

[00:12:49]Now, the word XOR means exclusive OR.

[00:12:54]Here, output will be one if input A is one or input B is one.

[00:13:01]Here, we are excluding the condition the output will be one when all inputs are one.

[00:13:08]Therefore, XOR gate is an exclusive OR.

[00:13:14]Now, to understand this in a better way, let's see the truth table.

[00:13:19]Here, we have four input combinations.

[00:13:21]Now, look at the first input combination. When both inputs A and B are equal to zero, which means both inputs A and B are same. Therefore, the output is zero.

[00:13:35]In the second input combination, when A is zero and B is one. So, here both inputs are different. Therefore, output is one. In the third input combination, when A is one, B is zero.

[00:13:50]Again, here we have different inputs.

[00:13:53]Therefore, output is one.

[00:13:56]In the last input combination, when A is one, B is one.

[00:14:01]So, both inputs are same. That's why output is zero.

[00:14:06]So, I hope you understand this truth table. Now, focus on these two input combinations for which the output is one. Now, in these two input combinations, there is a single one, which means odd number of one.

[00:14:25]So, whenever there are odd number of ones in the input combinations, the output will be one. So, the XOR gate is also called as odd ones detector. And I hope you understand this. Now, let's see the symbol for the XOR gate. Now, the symbol includes the same OR gate along with the curved line. Now, this extra curved line represents the exclusiveness of the XOR gate.

[00:14:54]So, I hope you understand the XOR gate.

[00:14:57]Now, let's see the second derived logic gate, which is XNOR gate.

[00:15:03]Now, XNOR gate is the inverse of the XOR gate, which means XNOR gate returns one when the inputs are same.

[00:15:15]So, output will be one when inputs are same. Let's understand this using the truth table. Here in the four input combinations, look at the first input combination. When A is zero and B is zero, which means both inputs are same.

[00:15:32]That's why the output is one.

[00:15:35]In the second and in the third input combinations, both input combinations have different inputs. Therefore, the output is zero. In the last input combination, both inputs A and B are equal to one. Therefore, the output is one.

[00:15:54]Now, in the case of the XOR gate, the outputs were 0 1 1 0.

[00:16:01]But, in the case of XNOR gate, the outputs are 1 0 0 1. So, XNOR gate is the opposite of the XOR gate. Now, let's see the symbol of the XNOR gate.

[00:16:17]Now, the symbol includes the XOR gate along with the bubble. So, XOR gate with inverted output.

[00:16:27]So, I hope you understand all seven logic gates. Now, let's implement them using Vivado with the help of data flow modeling using VHDL.

[00:16:39]So, we are in Vivado and this is the data flow modeling code for the seven logic gates. Now, if we want, we can change this light theme interface into a dark theme based on your Vivado version.

[00:16:55]For that, go to tools and select settings.

[00:17:00]Now, click on try the new Vivado IDE.

[00:17:04]Then, click on okay. Now, click on this Vivado setting as okay.

[00:17:10]Now, you just need to restart your software. Means, close the software and reopen it.

[00:17:17]Now, after restarting our software, this is our new Vivado IDE.

[00:17:22]Now, in order to change this light theme into a dark theme, go to tools, click on settings.

[00:17:31]On the left-hand side, in the tool settings, click on text editor, then select VHDL.

[00:17:41]Now, here we can see themes option.

[00:17:43]Currently, it is a light theme. Change this light theme into a dark theme.

[00:17:49]It will take only few seconds.

[00:17:52]Just wait.

[00:17:56]Now, this is our dark-themed interface.

[00:17:59]Close this notification. Now, let's get back to the VHDL code.

[00:18:05]Now, our code starts with IEEE library with standard logic package from the IEEE library. After library declaration, here we have entity. And here, I have named this entity as logic_gates.

[00:18:21]Now, inside the entity, we will declare the input and output ports. Now, as discussed in the presentation, we have understood two input AND gate, two input OR gate, two input NAND gate, two input NOR gate, two input XOR gate, two input XNOR gate, and a NOT gate. Therefore, I have declared here two inputs A and B as standard logic data type. And to represent the seven outputs of the seven logic gates, here I have represented the seven signals. And and_d is representing the output of AND gate as standard logic data type.

[00:19:04]Or_g signal is representing the output of an OR gate as standard logic data type. Not_g signal is representing the output of the not gate as standard logic data type. And similarly, here I have declared the remaining outputs.

[00:19:22]Now, we can close this entity with the keyword end and with the name of the entity logic_gates.

[00:19:30]After entity declaration, we will have our architecture.

[00:19:35]Architecture name as dataflow because we are writing the Boolean equations of logic_gates is and after the keyword begin, we can write the Boolean expressions using the logical operators. Here we are using seven logical operators: and operator, or operator, not operator, nand operator, nor operator, exor operator, and exnor operator to represent the Boolean expressions.

[00:20:05]Now, look at the first Boolean expression.

[00:20:08]A and B.

[00:20:10]We are assigning this A and B in the and_G signal.

[00:20:17]Similarly, A or B and storing the result inside the signal or_G.

[00:20:24]Not A means we are taking a complement of the signal A and storing the result inside the output signal not_G.

[00:20:34]In the same way, we can perform other Boolean expressions for the other logic gates as well.

[00:20:40]Now, I hope you understand this dataflow modeling code for all seven logic gates using the all seven logical operators.

[00:20:50]Now, let's see the schematic diagram generated by Vivado. For that, go to RTL analysis.

[00:20:58]Click on open elaborated design and select schematic.

[00:21:04]So, this This the schematic diagram generated by Vivado. Here we have two inputs, A and B, and seven outputs representing the seven outputs of the seven logic gates. Now, let's verify the schematic. Here, output and {underscore} g is equal to A and B.

[00:21:25]Output or {underscore} g is equal to A or B.

[00:21:31]Now, for NAND gate and NOR gate, Vivado does not have any specific symbols.

[00:21:38]Therefore, Vivado represents them using the complemented form of the AND gate and the complemented form of the OR gate. So, NAND {underscore} g is equal to the complement of A and B.

[00:21:55]NOR {underscore} g is equal to the complement of A or B.

[00:22:02]Now, the next output NOT {underscore} g is the complement of input signal A.

[00:22:10]Similarly, we can see XOR gate output and XNOR gate output. Here, XOR {underscore} g is equal to A XOR B.

[00:22:21]And XNOR {underscore} g is equal to A XNOR B.

[00:22:27]So, I hope you understand this schematic diagram. Now, in data flow modeling, the Boolean expressions are directly converted into the schematic diagram.

[00:22:39]Now, let's see the simulation waveforms generated by Vivado. For that, go to simulation, click on run simulation, and select run behavioral simulation.

[00:22:52]Now, this is our simulation waveform window. Here we have our two inputs, A and B, and seven outputs. Now, let us verify our VHDL code for all four input combinations. For that, let me quickly assign the input values manually.

[00:23:11]Now, how to do that? Let me show you.

[00:23:13]Right click on signal A, select force constant to apply the values manually.

[00:23:20]Now, select value radix as binary because we want to apply binary numbers zero and one.

[00:23:27]Now, force value zero.

[00:23:30]Then, click on okay. Similarly, for signal B, right click on signal B, select force constant.

[00:23:37]Value radix as binary. And force value as zero. Now, this is our first input combination zero zero.

[00:23:46]Similarly, you can assign other three input combinations as well. Let me quickly assign them.

[00:23:52]Now, I have assigned all four input combinations and I've simulated each input combination for 100 nanoseconds.

[00:24:00]Now, let's see the generated waveform.

[00:24:02]Let me maximize this waveform.

[00:24:05]And here we have all four input combinations.

[00:24:08]Zero zero. Zero one.

[00:24:10]One zero and one one.

[00:24:14]Now, let's verify our code for one input combination. Let's say for zero one.

[00:24:20]When A is equal to zero and B is equal to one.

[00:24:24]Now, what will be zero and one?

[00:24:29]It will be zero. And here we can see and underscore G is equal to zero, which is correct.

[00:24:37]Now, what will be zero or one?

[00:24:41]It will be one. And here we can see or underscore G is equal to one.

[00:24:47]Which is correct.

[00:24:49]Now, not of A, which is equal to not of zero.

[00:24:54]Which will be one.

[00:24:56]And here we can see not_g is equal to one.

[00:25:01]Now, what will be zero NAND one?

[00:25:05]It will be one. And here we can see NAND is equal to one.

[00:25:10]Now, what about zero NOR one?

[00:25:14]It should be zero. And here we can see NOR is equal to zero.

[00:25:19]Now, what about zero XOR one?

[00:25:23]Here we have a single one. And we all know that an XOR gate is the odd ones detector. Therefore, it will be one.

[00:25:34]And if XOR is one, XNOR will be zero.

[00:25:39]And here we can see XNOR is equal to zero.

[00:25:43]Which means our code is absolutely correct. And I hope you understand the implementation of all seven logic gates using data flow modeling in Vivado.

[00:25:55]So, in this lecture, we understood all seven logic gates. And we have also implemented them in Vivado using data flow modeling.

[00:26:04]With that, we are done with this topic of logic gates using VHDL in Vivado. So, we are done with this lecture. I will see you in the next one. Thank you.