Is This How China Bypasses US Sanctions?

Added: 2026-05-30

[00:00:00]Huawei shocked and surprised journalists when it announced that it hopes it will be able to make 1.4 nanometer class chips by the end of 2031. This is without access to EUV or new equipment due to export limitations and US sanctions.

[00:00:14]Huawei has proposed a new Tao scaling law or DAO depending on if you want to go into some Chinese culture that replaces um traditional geometric scaling or moors law.

[00:00:28]One of the techniques that they've shown in a recent talk at a conference, this is why this is all kicking off is called logic splitting. And we've already seen from other companies that such as AMD that there has been a road map of advanced packaging and scaling that we know this has been on the cards. Other semiconductor companies are looking into this but due to otherography tools uh namely EUV and higha uh enabling logic scaling things like logic splitting are on the back burner. Now with Huawei's inability uh with ESM to get anything more than modern DUV equipment, there is an effective scaling wall without excessive patterning um which has risk for misalignment and contamination as well as other factors. ESM and Huawei cannot feasibly get below what TSMC, Samsung and Intel foundry have been called 7 nanometer. Can they do it reliably? This is yet another iteration.

[00:01:21]But during the keynote in the talk uh hating b the person giving the presentation for Huawei announced that in the last six years they have mass-produced 381 chips in different sectors using this tow scaling philosophy. Though what was interesting is that the Kierin chips released to be released at the end of the year will apparently be using this logic splitting or what they're calling logic folding architecture already.

[00:01:46]It remains to be seen whether it can be done at scale.

[00:01:50]That's what we had in prepared remarks.

[00:01:52]Let me um bring this to the stage. This is the tweet that I think a lot of people saw. I mean, look, 31.7 million views. Um this is Tingbo from Huawei. Huawei presents that. So, it's it's it's three things here uh presented and it's important that you understand that they are distinct parts. One is the tow scaling law and we'll get into that in a second. One is that they through the method of the tow scaling by 2031 they will have a transistor density that is equivalent to 14 angstrom processes. Um which is still going to be a couple of years behind everybody else anyway if you assume that to be true. And the third one is this uh logic folding logic splitting technique.

[00:02:44]and we'll get into each of them. This is the tweet that most people saw and then this is the um official uh press release on the Huawei website. So, I'm not sure how many people were briefed on this, but uh people are rushing currently to get articles out to explain what this means and there's a lot of FUD um everywhere.

[00:03:09]So, let's start with the tow scaling law.

[00:03:14]Right? Yeah. So this is this is the tower scaling law. Right? Now to put this into perspective, Mo's law, whether you call it a law or whatever, um Moore's law is seen as a target in the industry to improve logic scaling.

[00:03:33]Now you can interpret the law in many different ways and people vehemently argue on this and I've I've I've covered this before but some people see as a doubling of transistor density every certain amount of months and years. Some see people see it as a increase in the number of transistors per chip.

[00:03:52]Uh some people see it as a number of transistors per package and some people see it as a economic law, right? As in it's all to do with transistor cost over time.

[00:04:06]Those are the four main ways to interpret Moore's law. I'm of the opinion that it's transistors per package because I find that as a useful tool to drive uh the process forward. Now the thing is Mo's law isn't the be all and end all, right? There's more to just simply improving your transistor density. There are things like packaging and design technology for optimization and uh TSMC has a thing called finlex where you can decide how many transistors are on your POS versus your NMOS. um and you optimize optimize different VT uh voltage uh temperature voltage frequency targets for your cells, right? And there's a whole array of techniques that we kind of all bundle under Moore's law because it gives a common view.

[00:05:01]Huawei's opinion because they no longer have access to the leading edge EUV and high AUV because they can't use TSMC or Samsung um or Intel because of US sanctions is that we need to redefine what our goals are.

[00:05:19]And their argument is that we're going to redefine this by ignoring Mo's law because we can't compete with that.

[00:05:26]still acknowledge it exists.

[00:05:29]But talk about tow scaling or dowo scaling or um yeah again it tao and dao in in in China has uh relevancies but the whole point here is that if you can improve your silicon in any way the device the circuit the chip or the system then you are following tower scaling.

[00:05:57]So it doesn't matter if it's just logic density, it could be SRAM density, it could be efficiency, it could be capacitance, it could be DTCO, it could be 2D, uh 2D, it could be 2 and a halfD, it could be 3D, right?

[00:06:10]>> But the that applies to like >> Yes, it applies to everything.

[00:06:17]>> Yeah.

[00:06:18]>> What what what they're trying to say is we think Mo's law is too narrow focused.

[00:06:23]Yet Moore's law has been a proxy for everything I've just said for decades.

[00:06:29]>> Yeah. You're you're fundamentally just trying to you're redefining a term in such a way that you're not changing the definition at all.

[00:06:39]>> A lot of media organizations have said that Huawei have turned the tables on >> western chip design because they've they're doing tower scaling rather than mos law scaling.

[00:06:52]It's the same thing.

[00:06:55]>> It's literally the same.

[00:06:56]>> PR PR uh corporate wants you to tell you the difference between these two pictures. It's the same picture.

[00:07:03]>> To be honest, let's let's get a meme of that and a t-shirt out.

[00:07:08]>> Um I I say Bloomberg because I did see their article, but a lot of other news outlets are saying this is revolutionary. This is and I've I've had an argument on this with Twitter with a couple of Chinese people already saying, you know, your western brain is too small to comprehend. It's not. It's just redefining the problem is rarely a breakthrough, right? And in this case, we know it's not a breakthrough because this is stuff that people have been doing again for decades, >> right? Logic scaling has been a part of that. their their whole argument here is let's focus less on logic scaling and focus more holistically at a system topology. This is all that slide says is we're considering tower scaling to be everything. And so when they say we've developed 381 chip was it 381 chips over the last six years in different sectors using this philosophy.

[00:08:06]By that definition, there's been millions of chips developed >> by this philosophy >> using that very same philosophy.

[00:08:13]>> Yes.

[00:08:15]>> So, it it's don't go don't go wrong, clever marketing. And if I was um if I was advising Huawei, um I would I I would say this isn't a bad idea. Per perhaps be a bit more humble about it because you're not redefining the view. you're refocusing the view, right? So the the the tower here is meant to be time and it's time to solution rather than transistors per square per square millimeter >> frequency >> or >> when I heard >> when I heard tow scaling my brain went to time scaling.

[00:08:56]>> Yeah.

[00:08:57]>> Like what >> it's it's it's no it's it's 2 pi scaling.

[00:09:03]>> Yeah. Yeah. That's exactly what it is.

[00:09:05]>> That's a t-shirt we need to make. It's got two pies on it and it says scaling.

[00:09:11]>> Oh, that's that's good.

[00:09:13]>> I'll fire up my AI models. Um >> the the next thing is this circuit folding that they're doing. Uh that what they call it logic folding architecture.

[00:09:30]Again, logic folding, logic stacking.

[00:09:33]Um, the best way I want to showcase this is by actually using AMD's slide.

[00:09:41]And I'll take the comments off the stage just so we can see it for a second. And AMD shows this slide off, I think, in hot chips 33, which is in back in 2021.

[00:09:52]And this was at a time where the concept of stacking chip on chip was just starting to become reality, right?

[00:10:01]already been in the works 10 years, right? E-IB the initial thoughts and patents filed in EIB were I think back in 2008, right? And EIB is a form of stacking technology, right? So 3D stacking uh you know this isn't pop stacking, right? This isn't 45 micron stacking like with cos we're talking about here hybrid bonding.

[00:10:28]What what typ typically it's called hybrid bonding or hbi where >> what what is what AMD now uses in vcash.

[00:10:37]>> Yes. So the the way this happens when you have copper bumps they're not bumps it's just it's just copper ends that you uh bond together from two chiplets. Um the idea is you do it without uh without balls so you can get the pitches finer and that and when it's using balls we just call it you know balls on balls bonding I microbumps. There we go. But I I'll keep saying balls on balls and laugh every time because I'm nine years old. Um but hybrid bonding doesn't use doesn't use the microbumps and it's a way to get uh denser connections but you need to design for it right and the first productization of this um so so uh just to clear up Intel's fauos the first gen first and second generation are microbump because they're 45 and 35 micron pitch AMD's first vcash and therefore TSMC's first hybrid bonding is 9 micron pitch. That means the distance between the center of two dot two two connections is 9 microns.

[00:11:45]Yeah. And when we talk about 10 nanometer obviously 10 is very very small. So 9 micron by comparison is huge but it's a way to combine chips together.

[00:11:56]And as we see here on AMD's diagram, you know, with nine micron pitches, you can do RAM on RAM on CPU, CPU on CPU. That's full D to die. And then they're going down here in the how interweaved can you put your design together. So going down, we've got IP on IP and then macro on macro where we're literally splitting up different parts of the CPU core uh onto different chips.

[00:12:28]IP folding and splitting where you're uh doing even individual parts of the IP blocks until we get fully to the end circuit slicing. Now as you go down, you need finer and finer and finer pitches. You need smaller and smaller micron size pitches.

[00:12:45]Um and as the reason why that is is because every time you go over one of these um connections you encounter a resistance and capacitance and you have to overcome that and the way you overcome that is by more and more connections running at lower and lower frequency right um and in terms of road map right now AMD vcache is at nine Intel's Fus Omni I believe is at like 9 or 8 and Samsung is doing Samsung things. Samsung doesn't do a good job marketing there. So, we'll leave that for a second. Both TSMC and Intel have road maps down to six, five, and four micron pictures. Right? In research we are down to 100 micron or even 10 sorry 100 nanometer even tens of nanometers in terms of bump pitches.

[00:13:45]The biggest problem between research and productization is moving it into volume because it you can do it once in a lab fine doing it 10 million times in a facility is problematic. Um, not only that, not only that, you need the tools to do it. The the the the thing with volume manufacturing though is uh the lithography to do hybrid bonding um is very different to lithog to standard leading edge lithography. One example is I was at a show this week, last week um where ASML presented some of their hybrid bonding solutions and the amount of energy you need to hybrid bond is per square cm is 10 times more than you need for uh leading edge EUV 3 2 nometer transistors, right? There's a lot of energy that goes into this. You got to which mean the fact that you're putting more energy in in means that it's also slower, right? because energy is a function of time in these processes. And then you've got to yield it at scale. You got to bond it at scale. Are you doing when you're bonding dyes together? Because this is all die on die, right? Do you pre do you test each individual die, do you do singulated die tests like Intel does so you know you're putting a good die with a good die or or or are you just um freeballing it? Are you just taking any dyes that come off and bond two together and see what happens? Or are you testing to make sure each die has worked so you put good with good and you can throw out the bad at that?

[00:15:24]So logic stacking from Huawei is 3D stacking in the conceptual sense but instead of having uh SRAMM on logic or logic on SRAM like we have AM and D their purpose is saying we're doing logic on logic and we're doing it at a two micron uh pitch which would be market leading significantly. ly and so I I'll throw up a couple of slides here that we have from the presentation. If anybody has access to the full presentation, please let me know. I'm still only getting rush slides. So what they're saying here is that the their smartphone chip, so this is a Kierin smartphone chip for 2026. We expect it's their leading edge chip is going to be using this 3D stacking design. what they're calling uh they're saying that logic folding is one step above beyond 3D stacking.

[00:16:24]Going back to the AMD slide, this is this is essentially going from the second one to the third or the fourth one. We expect it's more likely to be the third one because you need, you know, nanometer size gate pitch for right here at the end. What they're saying here is that with the Kirin 2026 um they can increase max frequency, they can increase their pecore power efficiency and that's fine because you can do triplets of different process nodes. We get that the max frequency we'll get to in a bit. The density here is annoying um because what they're doing is uh we when we talk about transistor density which is often a proxy for the quality of the node we're talking about transistors per unit area not per unit volume per unit area and that's what we're calling a density.

[00:17:21]It's a metric that has existed from the beginning of making chips because pretty much every chip we make is monolithic.

[00:17:32]Even today, pretty much every chip we make is monolithic. The problem becomes once you stack logic on logic because your total 2D space is now two layers but your physical XY dimensions of the chip have stayed the same.

[00:17:52]So if you're saying transistors per square millimeter are you talking about the floor plan or the silicon used?

[00:18:00]And the the thought experiment I put on Twitter was if you build a bungalow, a one floor house with three bedrooms, that means you have three bedrooms per unit house.

[00:18:15]If you now build a second story on that with another three bedrooms, has your density increased?

[00:18:26]>> Depends. The correct answer is in urban planning, yes.

[00:18:32]In construction, no.

[00:18:36]>> And what Huawei are doing here is the urban planning equivalent whereas the rest of the industry is construction the construction method.

[00:18:46]>> Yes. So >> because like for example when so I don't think this is a shock to anybody but I also write Okay. Um I also write for tech insights and whenever tech insights does uh a transistor like density measurement for for vcash for example they will do a a density measurement for the top die and a density measurement for the lower die. They don't granted that's logic on SRAMM not logic on logic but the same thought applies where it's it's really the density of the the dyes individually not the combination of the two. Um, so so so here's here here's my prop.

[00:19:37]Here is a Microsoft fungeible ASIC back when they used to do smart um smart uh smart network controllers back in 2019, >> right? Imagine this has 50 million transistors, right?

[00:19:55]>> Mhm. If I put five of them together, do I now have a chip that's 250 million?

[00:20:05]>> No.

[00:20:05]>> Or do I have five chips of 50?

[00:20:07]>> You have five chips of 50.

[00:20:09]>> So this is this is the argument on the transistor density. Right? So this is a diagram in the presentation talking about circuit folding about logic stacking.

[00:20:20]There are other problems you have. So the re one of the reasons why it probably is macro macro is because you have to do timing synchronization between layers right and that's difficult it's difficult to do it in a big chip to begin with um in you know in a big chip so if you suddenly have synchronized between layers you have to decide you know about your phase lock loops about your um about your buffers your transmitters your receivers about your SKUs how do we know it's two two micron and it's from this picture that somebody sent to me. Um, currently with all hybrid bonding solutions because of the capacitance and resistance and the extra time needed to cross that boundary, they're very they're not on the critical path. And by critical path, we're talking about the fastest way to get to a solution to a compute solution.

[00:21:19]Huawei is saying that through fan out they're able to reduce their hybrid bonding pitch to sub two micron. Now that's not to say as George pointed out that this is coming in the kirin later this year. This might be simply a the end goal. Um but this is what it has to look like and the pictures you might see are very much of this uh ilk, right? Um but if you can see when we're doing uh the interesting here is this is logic on logic right the hybrid bonds appear at the top of the metal stacks.

[00:22:00]>> Mhm.

[00:22:00]>> So what you've you've got here is a back to back.

[00:22:05]>> Yeah. Not a front to front >> or a front to back. Um >> yeah. So, where's the power being dissipated? At the top and at the bottom.

[00:22:18]And you've got the latency of the of the data to go all the way through the metal stack all the way up to the top. That might be negative.

[00:22:26]>> Yeah, that's it's something to look at.

[00:22:29]>> And the thing is is that the reason why TSMC and Intel want to do frontto is because then your critical path is not that long loop. It's right next to each other.

[00:22:42]>> Yeah. The the the the end result is they showed this, right? Uh so so so so here they're showing their transistor density versus their systems roadmap. Um and now there is there is some jiggory pokery on the density measurement. It is design utilization of 60%.

[00:23:05]Um but the jump here is 2025 to 2026.

[00:23:10]They're saying that their pecore frequency goes from 2.75 to 3.1 and we know that's been a limit of uh SMIC's 7 nanometer technology. Huawei's not being able to get above 3 GHz on it uh with their cores. The the density here goes from 155 to 238. Again, because we stacking two chips, bro, that's not the same thing as density.

[00:23:38]Come on. Um some people will argue if you uh read down here it probably does take that into account but I doubt it.

[00:23:48]But you also notice that 2030 to 2031 is also significant jump not only in frequency but also in transistor density.

[00:23:55]Uh >> like but also like if you look at that density >> that density equals two that's not a standard measurement.

[00:24:09]>> No to be honest density is a non-standard measurement for everyone.

[00:24:17]>> It it >> Well, isn't it just uh gate pitch time?

[00:24:22]>> No.

[00:24:22]>> No. Everybody has their own uh >> okay >> I remember Intel tried to redefine uh transis density by talking about ratios of uh flip-flops to other sorts of gates.

[00:24:36]So it's that sort of thing.

[00:24:40]Uh and then we come to the paper.

[00:24:44]This is on China's version of archive.

[00:24:46]So it's it also a presentation at conference. So it's not peer-reviewed.

[00:24:51]Um, and it's it's it's not a massive paper by any means. It's 16 pages. It's fairly high level.

[00:25:03]So, I I I started reading this and I think I got to the end of the first paragraph and I noticed something very peculiar.

[00:25:12]And this is something you notice if you work with it a lot. Now, I'm no stranger to AI. I use it as an assistive tool in a lot of what I do. Um, I'm mostly shouting at it and telling it it's doing things wrong. Um, so when so when the AI lords rise up, I'll be the first to go.

[00:25:32]No doubt.

[00:25:34]>> But when you use it as an assistant to writing a lot of things, um, you identify very specific ways in which things are written.

[00:25:47]that that that's a really shitty sentence. Um, you understand how it writes things.

[00:25:53]And one of the ways it writes things is, you know, everybody knows about the M dashes at this point. I think everybody who's who's deep into it. Um the the the the M dashes which are uh the super long dashes actually a common thing um in in um in Mac uh word processors. If you do a dash dash space it will do an M dash for you.

[00:26:22]Um but for some reason GPT and other LLMs do a lot of M dashes. What they also do is a lot of short stabby sentences.

[00:26:30]And so let me let me read it to you just so you can identify the short stabby sentences. For six decades, Moore's geometric scaling drove progress in semiconductors. The industry compact no longer holds. Returns from pure dimensional shrinking have flattened.

[00:26:45]Leading edge design budgets exceed $1 billion per chip and cost for transistor at the most advanced nodes is no longer falling.

[00:26:52]This perspective argues for a successor scaling principle tow scaling that adopts time itself rather than transistor area as the primary metric of progress applying a single characteristic time constant tow as the unifying optimization target across 12 orders of magnitude from a switching transistor to a data center workload.

[00:27:11]It's a short stabby sentences.

[00:27:15]No, but another thing that you could tell that this is written by an AI because I've used I've used chat GPT as like for editorial pass before just because I know that I can be very long and rambly in my sentences.

[00:27:29]>> Uh lists starting with a colon.

[00:27:32]>> Lots of those.

[00:27:35]>> It does like multiple sentences that have the A, B, and C format.

[00:27:41]Yes, >> that's another characteristic probably derived from having short stabby sentences. Um, it it's also it also enjoys doing what I call false binaries, which is it's not X, it's Y, or phrases of that nature. It's not that we can't see this, it's because of this. It's not it's not because it didn't work, it's because it did work.

[00:28:08]Um uh for example I'll read on this is just a screenshot but um it says you know for Huawei semiconductor this transition arrived with additional constraint restricted access to the most advanced lithography tooling assuming that another node would resolve the problem was no longer tenable. Six years ago the geometric road map plateaued forcing a more fundamental question one that in retrospect the entire industry will eventually have to confront.

[00:28:35]I mean, that's just all four of my big AI talking points all in one, right?

[00:28:40]>> Uhhuh.

[00:28:42]>> It it's Now, somebody did point out to me, maybe this is just because they wrote it in Chinese and they used an AI translation tool.

[00:28:51]The thing is, when you do that, sometimes you there's still mistakes. I haven't seen a English mistake in this.

[00:28:59]It uses a lot of words that a um AI likes to use. I'm pretty sure you've seen the graph of scientific research papers with the word delve in them has tripled in the last two years because delve is a very AI you know phrase.

[00:29:16]Let's delve into this things like plateaued especially as well. Um and the thing is because this paper is talking about some basic you know we we we saw with the towel scaling um that it was pretty holistic but they tried to put numbers to it. So logic folded so so up here is the SOC list.

[00:29:45]I've always advocated that chips should be called by the year they come out.

[00:29:49]Unfortunat unfortunately, you know, like cars, uh, but apparently none, nobody seems to like that. But logic folding at a glance, hybrid bonding pitch is sub 2 micron. So one and a half micron in 2026.

[00:30:03]That's crazy. That's market leading if true overlay accuracy. So, this is the how accurate can they be getting um because because what they'll probably do is um chip on wafer or wafer on wafer bonding then dice rather than chip on chip.

[00:30:20]>> I would it I would assume it's wafer on wafer.

[00:30:24]>> Yeah, >> the wafer on chip is also or chip on wafer is still possible.

[00:30:29]>> It it depends. They've not said anything about whether the chips are the same size, >> right?

[00:30:37]Um, but this overlay accuracy is essentially how accurate can they get it. Um, and you need it to be small enough such that regardless of how big your hybrid bond is, you'll always be in contact substantially because the less you're in contact, the higher resistance you are.

[00:30:54]>> Um, failure rate failure rate of 100 parts per million, repair rate 99.9%.

[00:31:01]Um, so what they're saying here is that they're building in enough redundancy so you don't just have one data line, you have four sort of thing just in case it's all screwed.

[00:31:13]>> Yeah, that's fairly standard.

[00:31:16]Um >> um but I will say an overlay accuracy of considering that they're saying under 0.5 micron >> for a point for a 1.5 micron pitch bond under.5 seems high I would expect under 0.1 >> it it's this is where the failure rate or repair rate and redundancy comes in. Um because you you expect all of your bonds to be in a specific XY location, but they might be plus minus um 10 nanometers.

[00:31:59]So imagine, you know, two it's it's like the it's like when they built the channel tunnel from France to the UK, >> right? there was a margin of error and I think the margin of error was probably as a fun as a as a fraction worse than this but you know you you try and do it. Um, uh, that tweeted all said 100% yield.

[00:32:25]Question mark question mark. This is just the hybrid bonding yield. Nothing to talk about frequency or shrew plots yet, right?

[00:32:36]Uh, so again, are they pre-esting chips?

[00:32:40]Um, yep. And we have um they've got a new interconnect to deal with this hybrid bonding. Um and then also at a later point they're going to put in optical IO which again isn't groundbreaking.

[00:33:00]Optical IO has been considered part of the let's move forward with Mo's law sort of thing for ages. It's because now they're saying tow scaling is everything. And there there's one thing that hasn't been addressed at all in any of this.

[00:33:16]Um, and that's thermals.

[00:33:21]One of the main issues of logic on logic is you're putting too much complicated stuff together, right? And now if you're dealing with say 40 nanometer, maybe you've got more headroom, but your performance is terrible because it's 40 nmter. If you're dealing with TSMC 7 nanometer equivalent, maybe you have thermal headroom. But as we said, if the bonding is back to back and you've got the compute on the top and the bottom of the two die, again, two die instead instead, let's put it turn this one around and say you have the heat on the top and the heat on the bottom. How you calling that?

[00:34:00]>> Um, you know, do you want to look into micrfluidics? Well, IBM has all the western patents on that. You just copy them, I guess. Um but it's a smartphone chip.

[00:34:12]>> Yeah.

[00:34:12]>> Um >> it shouldn't be that power hungry sustained.

[00:34:17]>> Well, no, no, no. So that's the chip as a whole, >> right? The problem isn't the peak consumption of the chip. It's the hotspots.

[00:34:25]>> Yeah.

[00:34:26]>> Right.

[00:34:26]>> It's the ALUS. It's the the FMAS. It's all those pipes. It's it's it's um you know if if we go back to our AMD image for a second when you've got macro and macro or even anything macro macro left when you design a 3D stack chip you have to be cognizant of what is on top of what because you need the thermals to work. If you put high compute on top of high compute you're screwed. This is often why critical paths are difficult to do in 3D stacking because a critical path just goes straight from the bottom to the top >> from the bottom transition on the bottom to the transistor on the top. That's why IP folding/splitting and the circuit slicing is very you know you end up with a very thermally dense solution because you're now putting you know 200 transistors instead of it being in a 2D block into a 3D cube. Um, and actually again AMD gave a at a synopsis thing, a presentation gave a really good talk about like how they had to do thermal design because so fun fact um, apparently MI300 was actually designed using rule thermal rules of thumb >> like not even like computer design because the tools didn't exist at the time. to be honest they still don't right >> well they they've started to become developed with like 3D blocks from synopsis >> but my point is is that >> okay Cadence announced that their virtuoso platform in the f you know using machine learning will support multi-d design rules >> and so you can split your chip your you know your macro and macro across multiple dies. Um, >> but again, you have to, you know, in a in thermal design in a smartphone with hot spots. So, somebody said, why couldn't they just use a me a MEMS's cooler because they're, you know, all the rage.

[00:36:39]Uh, mem's cooling is fun, but the efficiency is what, 85% at best.

[00:36:45]>> Yeah. Which is not at all sufficient for a phone. So for every seven watts you cool, that's one watt of power you need to power your cooling.

[00:36:57]Um, and the point is you have to think about this in terms of a smartphone. If you're in an automotive device, then you know pack it in, you know, some sub-zero thermal lubricant, whatever.

[00:37:10]Um, but in a smartphone, you're not. And this is and 3D stacking logic on logic is hard. at two micron bump pitch is going to be hard and not there so far they've not addressed the thermals on it.

[00:37:24]>> So in in chat Mayan 78 uh 31 says in the live stream in the Huawei live stream they mentioned thermals as part of future challenges.

[00:37:36]I'm sorry Huawei that's not a future challenge that's a now challenge. If you're going to be doing the 3D stacking, that is a now challenge.

[00:37:45]Again, referencing AMD, there's a reason why they went from logic on or SRAMM on logic to logic on SRAMM heat and removal of heat and all this fun stuff.

[00:37:58]>> It was it the thing is do but but put putting the computer on top is actually more problematic because you got to put all the power through the bottom chip.

[00:38:07]It makes all the communications to other chips longer and delayed.

[00:38:12]>> I've got a video on this.

[00:38:14]>> Like why why you know I wanted to call it the Australian CPU because it's upside down. Um but there's many reasons to not do it that way. The only one being relevant is thermals. Um so if I can share this. Where did it go? We actually did an article on um more on more than more um about putting HBM on logic and HBM4 >> has a has has a logic die on the bottom.

[00:38:50]So you're putting logic on logic before you're putting into memory and this is research TSMC has done. Right? Mhm.

[00:38:57]>> So instead of doing it in a 2 and a halfD like this, you put it on top 3D like this.

[00:39:03]>> And and actually uh Moshi, good friend of of both of us in the chat says, "No, you also don't get the cost savings of node scaling if you just slam two dyes together to get the increased density numbers."

[00:39:17]>> Yeah. Well, that that might be why it's not a double because one chip is on an older processor, right?

[00:39:22]>> And again, it's not true density. It's just transistors per chip per per package.

[00:39:30]>> Um, but yeah, no, if if you just plunk four HBMs onto a compute die in this scenario, you suddenly have some hotspots at 140 degrees.

[00:39:40]>> So, actually, uh, one of my favorite people to talk to, um, um, at Dell, uh, Travis was talking about the G the the cooling. Um, you can find images of it, but the cooling apparatus for their Dell Pro Max with GB300.

[00:40:02]I wish the name was better, but anyway, uh, is a single unit, right? But the but the important bit is that they actually cool, you would think that you would cool the GPU die first, but they don't.

[00:40:14]They cool the HBMs first because HBM actually has a reduced uh, max temperature relative to the logic, right? Think of think of laptops.

[00:40:24]They can go up to >> like modern Apple laptops. 115C and they they'll they'll happily go up to there, but HBM usually tops out around 85ish.

[00:40:37]>> Yeah, >> I believe is a spec.

[00:40:40]>> Well, so in this paper they said, well, if we do a bunch of stuff, we can get the temperature down to 17.8 degrees, right? Which is standard. Mhm.

[00:40:49]>> Um, one of the biggest drops that they had was one, merge the HBM together. So instead of four dyes, you have two.

[00:41:00]>> Mhm.

[00:41:00]>> And the other one was frequency scaling.

[00:41:02]Cut your frequency by half.

[00:41:07]The easiest way to drop the temperature is to drop the frequency. And Huawei has already said we're not dropping the frequency.

[00:41:12]>> Mhm.

[00:41:14]So yeah, how how you know how to call the 3D GPU stack on fire? Well, how how to call your smartphone on fire?

[00:41:24]>> At most three surfaces to dump heat into in a phone. You have the back cover, you have the screen, >> and you have >> the outside.

[00:41:37]Well, unironically, that is actually one of the heat sink like sinking heat into a hand from the sides is a is a tactic that you can do.

[00:41:50]>> Um, it's just you can't do a lot of that without causing problems, right? Mhm.

[00:41:59]>> Because while while your body will liquid cool the phone via your thermal interface material, that thermal interface material is not very efficient, nor is it u insensitive to significant heat.

[00:42:14]>> Yes.

[00:42:15]Um, it it's the problem that this whole story has is not that it's unbelievable, right?

[00:42:33]This whole thing about, you know, logic bonding, logic splitting, what have you, has been on road maps forever.

[00:42:42]The fact that tower scaling now just encompasses everything rather than just logic scaling isn't changing anything.

[00:42:49]Right?

[00:42:51]The big breakthrough here is Huawei claiming sub two micron hybrid bonding and logic on logic.

[00:43:01]Um, now I did have this argument online a little bit. Um, the yield issue, right?

[00:43:09]>> They've said that their hybrid bonding is effectively 100% yield because they've got failover and what have you, that's fine. Um, but when it comes to building chips, if they're using the same smic process as they've been using before, >> Mhm.

[00:43:25]>> then that's probably very well known and they can yield a good 80 90%. If their bonding on top of that is 100, then their overall yield is again and all it means is because they haven't had access to logic, they've decided to pull on one of the other threads a lot earlier than everybody else.

[00:43:46]You still need to scale that in terms of manufacturing. So, somebody pointed out to me that Huawei made 40 million smartphone chips last year. If they're going to sell the equivalent this year, they need to they need to hybrid bond that many.

[00:44:01]>> Well, they need to first make twice as many chips, assuming it's just two stacks of three. Because if you if you think about it, how many I realize ESMC ver I I realize ESM versus TSMC um or Samsung themselves, but how many S24s with or S25s or S26s with the latest Qualcomm or Exynos chip are sold?

[00:44:30]And that's just one device.

[00:44:33]>> It's not including iPhones. It's not including >> it. It's >> so so that's why I say that seems low in my head.

[00:44:41]>> Well, so one of the biggest um companies in the highway bonding space is a company called Bessie, right? And everybody's tracking them as a marker on uh leading edge equipment.

[00:44:57]And I'm I believe that they can't sell to SMIC, right? No. Because my question is who who's the Chinese equivalent of them and how have they gotten so far ahead? Now again, you could just argue because they haven't focused on logic, they've just put people on something else and they've just solved it quicker, right?

[00:45:19]Um if there's one company that is willing to accept lower yield, higher pricing in order to get massive volume, it's Huawei because of who packs Huawei.

[00:45:29]But also, Fuy makes a ton of money. They make more money now than they did pre- entity list stuff. Um, the whole 14A by 2030.

[00:45:43]Again, I I I bring out my construction stack, construction versus urban planning argument.

[00:45:52]It's you're you're you're arguing apples and oranges on that front. Um, >> yeah, >> they've presented this just before Computex.

[00:46:04]>> I don't think that's by chance.

[00:46:07]>> Is that Well, is this a coincidence?

[00:46:09]Because it happened at a IE conference.

[00:46:13]That just happened to be held in Shanghai the week before.

[00:46:18]My big issue is just how it's been promoted. People have taken it way people are saying this is an attack on TSMC.

[00:46:28]No, this is just one thing that it looks like if they've managed to succeed, they've done it well. They haven't answered everything. So, it'll be interesting to see how they do answer those things. Um, if any, you know, if anybody from Huawei wants to reach out and give have a chat, bring me up, right? happily h happily have a talk to understand what's going on. Um I don't like the fact that the paper's AI generated. Um I I maybe I'm more angry with just the generic response to all this.

[00:47:07]Now that I've actually spoken through it, I think I'm calmer.

[00:47:13]>> That's good.

[00:47:15]>> Now my beef isn't necessarily with Huawei.

[00:47:20]No, I think my Yeah, I think I agree that my beef isn't necessarily with Huawei. I think it's the way that certain people are presenting this.

[00:47:30]>> It's It's Everybody claims to be a semiconductor expert on Twitter.