Data Objects in VHDL

Añadido: 2026-05-18

[00:00:00]Hello everyone, welcome to Neso Academy.

[00:00:04]Till now we have completed two chapters in VHDL.

[00:00:08]The first was introduction to VHDL.

[00:00:11]In which we understood the basics of VHDL.

[00:00:15]And in the previous chapter we studied the structure of VHDL.

[00:00:19]Where we learned about library, entity, architecture and other design units.

[00:00:26]Now today we are starting a new chapter called data types and data objects.

[00:00:32]And in this lecture we are going to understand data objects.

[00:00:37]So, in this lecture we will cover only one topic. Which is data objects.

[00:00:46]To understand this, let me ask you a question.

[00:00:49]In any digital system, what we actually deal with?

[00:00:54]We deal with data, right?

[00:00:57]Zero and one, numbers, signals.

[00:01:01]And obviously, we need something to store and handle this data in VHDL.

[00:01:07]And that is done using data objects.

[00:01:12]So, let's see its definition.

[00:01:15]Data objects are the named items used to store values in a design.

[00:01:23]Means data objects are used to store values of a specific data type.

[00:01:31]In simple terms, data objects are used to store data in VHDL.

[00:01:37]And in VHDL there are different ways to store data values.

[00:01:42]Mainly, signals, variables and constants.

[00:01:49]Each behaves differently.

[00:01:51]And understanding this difference is very important.

[00:01:55]So, let's understand each of them separately.

[00:02:00]Let's start with signals.

[00:02:03]Signals represent a physical hardware connection or wire.

[00:02:10]Means signals behaves as a physical hardware connection or wire.

[00:02:16]Now, what does wire actually do in real circuits?

[00:02:21]It carries values.

[00:02:24]It transport data between different components.

[00:02:27]Now, signals not actually storing data like a real hard drive.

[00:02:32]Rather, it holds a value. Example, a voltage value.

[00:02:38]So, signal always holds a current logic value at any given time.

[00:02:45]Means signals hold a specific logic value.

[00:02:50]That is at any moment of time, signal holds a specific logic value, either logic zero, logic one, or any other definite value.

[00:03:01]To understand this, consider a physical wire.

[00:03:05]Now, what it will hold?

[00:03:07]It will hold low voltage, high voltage, or any other specific voltage, but a definite voltage at any given time.

[00:03:16]So, signals hold a specific voltage or a specific value at any given time.

[00:03:24]Signals, when a new value is assigned, updates occur after a delta delay, not immediately.

[00:03:34]Means when we assign a new value to a signal, it does not change instantly.

[00:03:41]Means it takes some time. So, updates occur after a delta delay.

[00:03:49]Now, what is a delta delay?

[00:03:52]Delta means infinitely small time.

[00:03:55]So, when we apply a new value to a signal, it will change after a delta delay, not instantly.

[00:04:05]And signals are used for communication between concurrent processes.

[00:04:12]That is, signals are used for communication between parallel processes.

[00:04:19]We all know in VHDL, multiple processes run in parallel. That is, at the same time.

[00:04:26]And signals act like wires, which connect these different processes.

[00:04:32]Means, if one process writes or assign a value, at the same time other processes will read that value.

[00:04:41]So, signals transfer data between parallel processes, just like wires connect different parts of a circuit.

[00:04:50]Where one part sends a voltage, and other parts read that voltage at the same time.

[00:04:57]So, signal transfer data between concurrent processes.

[00:05:02]Now, where we can declare signals?

[00:05:05]We can declare signals in entity, architecture, package, etc. So, signals can be declared in entity, architecture, package, etc. Now, let's see for example, how to declare signals.

[00:05:23]Let's try to understand how to store a logic zero or logic one value inside a signal.

[00:05:31]First, we need to use the keyword signal to declare any signal.

[00:05:37]Signal named A.

[00:05:39]I'm taking my signal name as A.

[00:05:42]Colon, bit, semicolon.

[00:05:45]Semicolon is used to end the statement.

[00:05:49]Bit is a data type which stores logic zero or logic one value, means a binary value.

[00:05:57]Overall, signal named A can store a logic zero or logic one value.

[00:06:06]What if I want to store a sequence of bits?

[00:06:09]That is an array inside a signal.

[00:06:13]How to do that? Let's see.

[00:06:17]We are defining a signal named data as bit vector bracket seven down to zero bracket close semicolon.

[00:06:28]This bit vector is a data type which represents sequence of bits, that is an array.

[00:06:35]And seven down to zero represents the length of an array. Here, it is eight bit.

[00:06:42]So, we are declaring a signal named data which can store an eight bit vector or an eight bit array.

[00:06:53]We have seen what is a delta delay.

[00:06:57]So, the question is, can we store a time delay inside signal?

[00:07:02]Let's see.

[00:07:05]We need to declare a signal named delay.

[00:07:08]And we are using a special keyword time colon equals to 10 nanosecond.

[00:07:15]This special keyword time represents simulation delay.

[00:07:20]And colon equals to helps to give initial value immediately.

[00:07:26]And what is the initial value?

[00:07:28]10 nanosecond.

[00:07:30]So, here we are declaring a signal named delay which can store a time value. And the initial value we are assigning is 10 nanosecond.

[00:07:42]So, I hope you understand these three examples.

[00:07:46]But, there is one doubt. Do we need to use this keyword signal every time to declare a signal?

[00:07:53]No.

[00:07:54]We have already seen in AND gate's VHDL code where we declared input signals A, {comma} B, and output signal Y without using the keyword signal.

[00:08:07]Using signal assignment operator.

[00:08:10]Let's see how.

[00:08:13]Here, we are using signal assignment operator.

[00:08:17]This less than equals to called as signal assignment operator.

[00:08:22]Which is used to assign a fixed value to signal A.

[00:08:27]Now, this value will update after a delta delay. So, we can directly use a signal assignment operator to assign a value to signal A without using a keyword signal.

[00:08:42]So, I hope you understand what are signals.

[00:08:45]Signals represent a physical wire which updates after a delta delay.

[00:08:51]Now, let's see the second data object, variables.

[00:08:56]Variables are used for temporary storage inside a process or subprograms.

[00:09:04]Means, variables are like temporary box which can store a value.

[00:09:10]Variables does not represent any physical structure like signals.

[00:09:15]Variables are used for temporary storage. And where we can declare variables? Inside a process or subprograms.

[00:09:26]We have already seen what is a process.

[00:09:30]A process is used to declare sequential statements such as if-else condition inside an architecture.

[00:09:38]So, we can declare variables inside a process or subprograms.

[00:09:46]As the name suggests, subprograms.

[00:09:50]Subprogram act as a program within a program.

[00:09:54]That is, it is a reusable block of code.

[00:09:57]Example, functions or procedures. So, we can use this subprogram in our code whenever we need it.

[00:10:06]And variables hold one value at a time, which can be changed as needed.

[00:10:14]Means, at any moment, variables can store one specific value, which can be changed as needed.

[00:10:23]Consider an example named variable A that can store fixed integer value eight. Now, the same variable A can store another integer value 10.

[00:10:34]But, not at the same time. So, variables can hold one value at a time, which can be changed whenever we want.

[00:10:45]And when a value is assigned, it updates immediately.

[00:10:50]Means, when we assign a new value to a variable, it updates immediately. Not like signals, which takes a certain delay.

[00:11:01]So, the question is, which one is faster? Signals or variables?

[00:11:06]And the answer is variables.

[00:11:10]Let's see few examples.

[00:11:13]In case of signals, we used a keyword signal to declare it.

[00:11:18]Similarly, in variables, we need a special keyword variable.

[00:11:24]So, we use a keyword variable to declare variable A.

[00:11:29]And here we are declaring a variable A that can store any integer value.

[00:11:35]But, we are not assigning any specific value.

[00:11:39]Let's see how to do that.

[00:11:42]So, we are declaring a variable named count and assigning a fixed integer value zero to this variable count.

[00:11:52]Now, other way to declare a variable without using a keyword variable is by using variable assignment operator.

[00:12:03]So, here we are assigning A to A plus one using this variable assignment operator.

[00:12:11]Colon equals to is called as variable assignment operator, which is used to assign immediate values.

[00:12:20]Which means, if I write this statement twice, A is assigned A plus one.

[00:12:27]Will it increase by two immediately?

[00:12:31]Yes, because variables update instantly.

[00:12:36]So, I hope you understand what are variables.

[00:12:39]Let's understand the third data object, constants.

[00:12:45]Constant stores a fixed value that never changes.

[00:12:49]Means, constants are used to store fixed values, which is defined once and cannot be modified later.

[00:12:59]Means, constants are used to store fixed parameters like width, size, limits, etc. Let's see one example of constant.

[00:13:10]We have already seen how to declare a constant inside a package model.

[00:13:15]Let's take the same example.

[00:13:18]So, we can declare a constant named width using the keyword constant.

[00:13:25]And here we are assigning a fixed integer value eight and inside this constant width.

[00:13:33]So, I hope you understand what are constants.

[00:13:37]Till now we have seen the three main data object of VHDL.

[00:13:42]Signals, variables, and constants.

[00:13:45]But, there is one more data object in VHDL called file.

[00:13:51]A file is used to read data from external files or write data to external files.

[00:13:58]It is mainly used in test benches for providing input data and for storing output results.

[00:14:06]We will see about this data object file in our test bench chapter in much more detail.

[00:14:12]Which means we are done with this topic.

[00:14:15]Data objects.

[00:14:17]To summarize this, signals behave like a physical wire which updates after a delay.

[00:14:23]Variables are temporary box which updates immediately and constants are fixed values which cannot be changed.

[00:14:31]So, we are done with this lecture. I will see you in the next one. Thank you.

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