VHDL Design Units

Hinzugefügt: 2026-05-10

[00:00:00]Hello everyone, welcome to Neso Academy.

[00:00:04]Till now we have completed the major parts of a VHDL code. That is library, entity, and architecture.

[00:00:13]But, in real designs, there are some additional components that we use whenever required.

[00:00:20]So, entity, architecture, and these additional components are the building blocks of a VHDL code.

[00:00:29]And they are called as design units.

[00:00:33]So, today's lecture is all about design units.

[00:00:38]In this lecture, we will cover only one topic, which is design units. And in this topic, we will see what are design units and their types. So, let's start the lecture without any further delay.

[00:00:56]Now, design units are the building blocks of a VHDL program.

[00:01:02]So, in VHDL program, a digital system is organized into distinct building blocks.

[00:01:11]In simple terms, a VHDL code can be broken down into smaller, manageable components known as design units.

[00:01:22]And these units can be compiled independently and stored in a library.

[00:01:29]Means, these design units can be saved separately and stored in a library.

[00:01:36]So, in VHDL, we can write an independent block of code that can be saved inside a library.

[00:01:45]For example, we can write a VHDL code for a package declaration and package body.

[00:01:52]Then, we can compile them together and stored inside a library.

[00:01:57]Now, let's see different types of building blocks, means different types of design units.

[00:02:05]There are five types of design units.

[00:02:09]Entity declaration, architecture body, configuration declaration, package declaration, and package body.

[00:02:19]So, let's see them one by one.

[00:02:22]The very first is entity declaration.

[00:02:25]Now, we have already covered entity and architecture in detail. And we know what is entity.

[00:02:33]Entity tells what the system is. So, overall, entity defines inputs and output ports that describes the interface.

[00:02:44]Means entity tells the external view of the system.

[00:02:49]Consider entity as a black box, which describes inputs and outputs of a system, where no logic is defined. Means entity doesn't define any internal logic.

[00:03:07]So, where we write these internal logics or the internal circuit?

[00:03:12]Inside the architecture. So, architecture describes how the design works internally.

[00:03:21]If entity is a black box, then architecture tells what's inside that black box.

[00:03:28]Means architecture tells the internal structure of a system.

[00:03:34]Architecture contains the actual logic.

[00:03:37]Means architecture contains the real circuit or real logic definition.

[00:03:43]We have already seen an example of AND gate. So, in entity, we describe the inputs and outputs of AND gate. Example, we will define A {comma} B as input signals and Y as output signal.

[00:04:02]And inside the architecture, we will write the real logic circuit or the real logic definition of AND gate.

[00:04:10]So, overall, entity tells what the system is and architecture tells how the system is created.

[00:04:19]Now, let's see the third design unit, which is configuration declaration.

[00:04:26]So, configuration declaration selects which architecture to use for an entity.

[00:04:34]In the previous lectures, we have seen that one entity can have multiple architectures. So, configuration is used to select which architecture will be used for an entity.

[00:04:47]Overall, configuration connects an entity with its architecture.

[00:04:53]Now, one entity can have multiple architectures and each architecture describes the system in different ways.

[00:05:02]And configuration is used to select one of these different ways.

[00:05:07]So, overall, if an entity has multiple architectures, configuration is used to select one of the architecture.

[00:05:15]So, I hope you understand configuration declaration. Now, let's see the fourth design unit, which is package declaration.

[00:05:25]Package declaration declares reusable items like types, constants, functions, etc. Now, package declaration is used to store common or reusable items that can be used in multiple designs. Means, package declaration is used to store reusable items like data types, constants, functions, procedures, etc. And why do we need this package declaration?

[00:05:59]To avoid rewriting of the code again and again.

[00:06:04]To make the designs reusable.

[00:06:06]So overall, package declaration specifies what is available to use. Now this is very important point.

[00:06:15]Package declaration only declare what is available to reuse and not the actual logic of the items.

[00:06:25]Now where we define the actual logic?

[00:06:28]Inside package body.

[00:06:31]So package body defines the actual implementation of functions, procedures, etc. Now what is function and procedure?

[00:06:44]Function is a reusable block of code that take one or more input parameters, performs a calculation, and return one actual value.

[00:06:56]While procedure is a reusable block of code that perform multiple operations such as updating signals or variables and can give multiple outputs.

[00:07:09]So package body defines the actual implementation of the items declared inside the package.

[00:07:18]Next point.

[00:07:20]Package body works together with the package declaration.

[00:07:25]Now package declaration alone is not enough. We need a proper actual logic.

[00:07:31]So package body works together with the package declaration.

[00:07:36]Overall, package declaration tells what is available to use and package body tells how it actually works.

[00:07:45]But remember, packages are mainly used for reusability and not for defining hardware directly.

[00:07:54]In simple words, to understand this, package declaration is similar to entity where both defines what is available to use and package body is similar to architecture where both defines how the system actually works.

[00:08:13]So, I hope you understand the different types of design units properly.

[00:08:19]Which means we are done with this topic, design units.

[00:08:24]So, a VHDL design is made up of multiple design units, each having a specific role and together they describe the hardware.

[00:08:35]In upcoming lectures, we will see the syntax of each of these design units in details, which means we are done with this lecture. I will see you in the next one. Thank you.

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