Course : UVM in Systemverilog 1: L4.1 : Generic UVM Testbench Structure

[00:00:00]a generic uvm based expansion this is a generalized uvm based response diagram in the previous session you have learned that you need to write your own test environment agent and some other classes in order to write your complete uv based test bench and this diagram shows how will you place all of these components in the test bench so if you see closely this is your design under tester duty this is your uvm based test class so you will be instantiating all of your uvm base components within a uvm based test class and you finally will instantiate your uvm test class and duty in the top this testbench module or the top module so this even though this is written as a uvm test punch this is a general system will log module which is instantiating both this duty and the final uvm test class now we'll see what what are the components in the test class within your own uvm based test class you will have your new vm based environment class so remember that this um test is you you are on uvm plus which is extending from the um underscore test class and this ui environment will be your own env which is extending from the uv underscore env class and so on and the test class will contain and the env class and within the environment there will be multiple agents there could be one or more agents and this is the uvm based as in class and also it is not shown here in in a uv imaging there will be three kind of categories of classes which is the driver class the monitor class and sequencer class so the sequencer driver and monitor all together will be instantiated within an agent class and multiple agents could be instantiated within an environment class and multiple environment classes could be instantiated within a test class and there will be only final single test class which is running a trip in a particular simulation and thus that is a final uh uvm based test class which is instantiating in the top level module along with the duty if you have noticed here the sequence classes will be running within from the test class you can ignore the configuration uh or factory classes for for the time b but note that the sequences will also be starting from the test class and the sequence class will again consist of multiple transactions classes and there could be multiple sequences running from the same test class another thing that i wanted you to notice here is that the duty is directly interacting only with an agent in a uvm based response to be more specific the duit will be interacting only with a driver and monitor class within an engine in it in a uvm based test bench none of the other classes like the test environment even the agents class the sequence any transactions or even the sequencer will not have any direct interactions with the design under test or the duty only the driver class and the monitor class which are sitting within the agent class will be interacting with the duty in a uv-based response here is a quick summary of a generic uvm based test bench your test class will encapsulate all other your own derived uvm based classes which are like the environment and sequence classes and the environment will be consisting of one or more uvm agents which again are consist of driver sequencer and monitor classes and along with your duty and design under test module you will be instantiating your uvm base test class within the top level module which is a system verilog specific module