Test compression is a technique that reduces test data volume and application time while maintaining test coverage by inserting decompression logic at scan inputs and compression logic at scan outputs, addressing challenges of growing IC complexity, increased test patterns, and limited test equipment capabilities.
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What is Compression?Added:
So what is compression? Compression is a technique of reducing test data volume and test application time while retaining the test coverage of your design. Inserting the compression logic requires ATPG capabilities and compression logic to insert on the input and output side of the design. Again it adds the decompression logic at the scan input side and at the scan output side it adds the compressor. Now the question is why you need to go for compression logic insertion when integrated circuit size grows. In today's scenarios, the ATPG vector takes up lots of AT memory and test time. Along with this, there is an increase in the number of test patterns. Newer chips often have more pins and functionality that cannot be handled by older AT equipment which have both a limited number of pins and limited buffer memory. Also, traditional AT tools might not have enough test pins available to take care of the current pin equipment and test cost also increases due to all these factors. So, what is the solution? You can use certain ways to take care of runtime and data volume like increase the number of the scan chains but it may increase the pin needed. Another solution is to increase the frequency of shifting patterns but it may increase test power. You can reduce the number of patterns but it impacts the test coverage. You can try signature-based output verification and again they are hard to diagnose. You can go for self- test logic bist but they are overhead and less control over the coverage. So what is the best solution that you can use? Yes, by using test compression we can reduce the AT test times and test data volume without compromising the design's test coverage. So by using test compression you can reduce the AT test times and test data volume without compromising the design's test coverage. Here we are showing the basic architecture of a test compression logic. Inserting compression logic involves adding a decompressor and compressor. The tool can insert a broadcast scan and an optional exorbased test input spreader for test data decompression. For the test output data compression, the tool can insert an exorbased or MISRbased compressor or a variation of these types. So this is how the cycle works. You take compressed data from the AT tool and you can expand or decompress it in on the chip and feed it into the internal scan channels available here. Collect the response data from the output of the internal scan channels and compact it into an output stream. And then you can send the compressed response back to AT for comparison to the expected responses.
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