FPGA Based 5-Stage Pipeline RISC Architecture Using Basys 3 Artix-7 Board

追加: 2026-05-26

[00:00:00]Okay, we are doing a logical operation.

[00:00:03]These two are the switches.

[00:00:05]So, like A and B. So, we are given V 17 and V16. These are the two inputs.

[00:00:13]Then outputs are U16, E19, V19, then U19.

[00:00:22]So, according to your logical operation, so when these two inputs are 0 0, so only not get. So, means A This is the A input. So, A input is 0 means we'll get the output is 1.

[00:00:37]Then 0 1.

[00:00:42]So, you'll get the AND operation, that is 0 1 means that is 0. So, remaining OR gate is output is 0 1. 0 1 mean 1.

[00:00:52]Then XOR is 1. Then not get A still A is 0, that's why that is 1.

[00:00:58]Next. So, next combination is 1 and 0.

[00:01:01]So, 1 and 0 means still OR gate AND gate is 0. OR gate is 1 because of one input is 1. Then XOR is not equal, that's why that is 1. So, A is 1 means output fourth in not gate is 0.

[00:01:16]Then last operation, that is with the combination 1 and 1. So, first AND operation. So, 1 1 means you'll get the output 1. OR is also 1 1 because of any one of the input is 1, so output is 1.

[00:01:29]Then next XOR both are equal means output is 0. Then A is 1, so output is 0.

[00:01:35]So, this is your entire logical operation using this basis 3 board using 3 board.