A CPU Made of Atoms: IBM's Breakthrough 0.7nm Transistors

[00:00:00]So, where do you sit with Moors law? If you go ask Nvidia, they'll say it's dead. Go ask the Moore company, Intel, they'll say, "Yep, alive and kicking."

[00:00:09]Go ask TSMC and they'll say something like, >> "I don't care."

[00:00:12]>> The company we're speaking about today, IBM, is firmly in the camp of yes to Moaw. Scaling does exist with transistors. And they're showcasing that with their new announcement of 7A nanoack transistors.

[00:00:28]If that sounds like a mouthful, well, let's break it down. 7A 7 angstrom or 0.7 nanometer is the name they've given to this process node technology. Now, you may remember names don't mean much in this day and age. It's the dimension in which if it was still 2D, this is what it would be like. But right now, it's just a name. But a name where the smaller number usually means better.

[00:00:54]Now, nano stack, this is where the technology is different to what everybody else offers in the market.

[00:01:00]It's an evolution of a concept that everybody's known about for a long time, what we're finally seeing demonstrated in production, or at least in manufacturing. High volume manufacturing comes later. And in this video, we're going to get down into why IBM calls their 0.7A nano stack the revolution the industry needs. Or actually, that might be my phrase.

[00:01:30]So for a start, let's just go back. And I know for some of you, you'll know a lot of this. What exactly is a transistor? Well, you have your source, your drain, your gate, and your channel material. The point is that over the years we've developed new ways of building transistors to help drive frequency, current, performance, and efficiency. We went from planer to finfet back I think the first finfet product was 2012 from uh Intel, but the research had been going on for quite a long time. And the idea was you make your planer transistor three-dimensional to help enable higher amounts of drive cover current that allowed us to scale in frequency and in density. Now FinFET had a good run. We went from about 22 nanometer down to 14 10 7 and in some cases even four with just FinFET technology. And over those years multiple generations bought many advances in scaling both logic and memory but also increases in performance and efficiency. This is why you can get 6 GHz processors now. But finfet had a limited run and next came gate allaround technology. This is essentially as if you took your finfet but chopped it up a bit.

[00:02:51]This allows for even more drive current, even more control over your transistor.

[00:02:58]And the first company to showcase this in a production level technology was IBM. You may remember this video I did back in 2021 when they announced the first gate allaround transistors and a two nanometer type of process node. Now in that video we discussed what the benefits were to going for gate all around but also some of the key metrics things like 333 million transistors per square me per square millimeter and what that would mean for the technology. Now the way IBM works is that they develop process node technologies and then license them out.

[00:03:37]the other companies in the foundry space, the ones that you uh know and love, TSMC, Intel, Samsung, they go and develop these technologies as well. And we often see lots of research papers at the conferences in order to enable this years and years out. We've been seeing what's coming up for example uh even as early as 2021 when gay allaround from IBM became news [snorts] and it's taken from 21 to about 2025 for that technology to go from uh production level to production ready.

[00:04:14]Now, if you ignore the fact that Samsung said that they technically shipped gate all around in 2022 to some Bitcoin mining company, the first real products with Gate Around came out in 20 late 2025. We've got Intel's uh Panther Lake, uh Clearwater Forest, and the Samsung Exynos 2600. TSMC still has to make their first commercial product with gate allaround technology. We're expecting that to be AMD's uh Zen6 Venice later this year. But it's taken 5 years from IBM to say we've got the process down for it to hit volume manufacturing. And that's just how the time scales in this industry works. Now it should be said that none of them are using IBM technology. They all develop their own.

[00:04:56]The company that is using IBM technology is a firm called Rapidus. This is a new uh technology foundry appearing in Japan. We've done a couple of videos on them already. We're really excited to see what their new fabin chtose uh can do with IBM's technology. But IBM still developed a number of key patents around the technology that gets put into all of these processes. So today's announcement is what comes after gate all around this sort of nano stack feature which means that if we were to talk about timelines we're realistically talking around 2031 at the earliest though I'm a little bit apprehensive about that and I'll tell you why.

[00:05:34]Gate All around is currently in its first generation technology. We're expecting gate around to last at least three or four generations before needing this new nano stack and it's going to take time for the foundaries to build in the gate all-around technology and time to develop and optimize. You'll hear something called fork sheet mentioned here and there as well. It's a type of gate all around. What IBM have done with this nano stack is developed what's something what some what a lot of people in the industry called is a CFET or complimentary FET and in order to explain how this work we have to explain the difference between an NOS and a POS transistor.

[00:06:11]The simple way of going about it is in one you have extra electrons and in the other you have extra holes and you in a CMOS transistor. So most technology we build today is called CMOS complimentary metal oxide semiconductor. The complimentary part is that you pair NOS with POS two transistors to get um a device that you can build um processes with.

[00:06:39]And so with complimentary FET what we have is an NMOS transistor and a POS transistor. Normally in gate all around we'd put them side by side. What complimentary fat does is put them one on top of each other or actually it's one on top of each other. Um and as a result we get a massive increase in density because instead of putting transistors side by side we're now doubling them up one on top of each other. This has been like I say in the research uh arena for quite a long while. Uh just simply talking about the materials and the manufacturing steps to get there. What IBM are saying is that they have now built the technology in a way that could be used for high volume manufacturing that showcases the performance and power characteristics of something that could be taken to high volume manufacturing. And they've got a lot of test examples and everything else. That's their big announcement today. What it comes down to is actually two research papers. one that they published last year detailing most of this and one that they've published recently at an event talking about how they're scaling their SRAMM technology because one big question as we go down the process node uh stack is how do we scale the SRAMM now if you want the full deep dive into all of this I have an article over on my substack more.com there will be a link in the description if you'd rather read about this uh but for this video I'm still going to go through the same points because they really do matter.

[00:08:11]Now with complimentary FETSS there are typically seen as two ways in which the research can go. One is called a monolithic complimentary FET and the key word there is the monolithic part. What happens is you build your NMOS gate allaround design and then on top of that you then build your POS design. So that almost sounds pretty simple. You build an N, then you build a P. Part of the problem is whatever you build on top, whether it's N on P, N on P or P on N or whatever way around, the thermal environment, the processing steps you need to do on the top can't interfere with what you've built at the bottom.

[00:08:53]Um, so if you have say a high temperature annealing step that needs 1500°, but it absolutely trashes your transistor below on your wafer design, then it's a no-go. you have to develop low temperature ways in order to do that.

[00:09:08]The contrast to the monolithic complimentary fat is the sequential uh complimentary fat where the idea is that you build your NMOS and your POS on different wafers and then you bind them, you stack them, you bond them together and that's what's called a sequential uh CF fet or an SC FET. The acronyms get very uh crazy. you'll agree the thing is IBM's not really doing either of those.

[00:09:39]Um, and we need to go one layer deeper and talk about well what makes a good NOS or POS transistor.

[00:09:48]Now with your transistor you have your channel material, you have your gate material uh that's built in and that is usually silicon. The thing is silicon isn't a regular latis of silicon atoms.

[00:10:00]Now if you have ever studied any form of solid state structure physics uh you may understand that sodium chloride standard salt is a very regular latice. It's essentially a a cubic latice. I believe they call it all allsided cubic latice um of sodium ions and calcium ions. The idea being that if you cut along any of the axes X, Y, and Z, you'll get the same um plane and which means that you'll see the same um atoms in the same layout as you cut through. With other materials though, they don't fit into that nice neat box.

[00:10:42]And to be honest, even with sodium chloride, if you cut at a diagonal angle, you'll see a different style of face compared to you would along the axis. And it just so transpires that the way you cut the silicon, the way you or in in this case you actually grow it epitaxially, the way you grow the silicon affects the performance of your transistors. And Moss prefers one way of doing it. Poss.

[00:11:08]And this is where you may come across terms like Miller indices. Now, when you're building a standard transistor design with uh NOS and POS transistors, you're usually limited to one direction, one plane for your silicon for both. And it's ultimately a compromise. It either favors one and not the other or favors the other and not the one or it's just bad for both.

[00:11:34]Same true with monolithic complimentary FETSS. With sequential CF fats, when you're reusing two different wafers, you could build them in different latis modes essentially. Then when you combine them, you get the best of both.

[00:11:51]Again, what IBM here doing here is kind of that for sequential FETSS, but kind of not. What you do, what IBM does is they build the NOS or the POS on one transistor uh on one wafer and then on the other wafer they build the silicon crystal latice first. Then they bond it on top and so all you have is the lattice. They remove the carrier wafer and then they build the top transistor in. So, it's like a sequential because you're using two two wafers to to bring the latis over, but then it's like monolithic because you're still building on top. And you might think, well, isn't that the worst of both worlds? Well, one, you get the latis you want for the transistor you want, which is good. Two, IBM say that they've for this process, they've solved a number of issues around the thermal so to to get it to work. And three, before I said a C fet is one transistor on top of another. What they're doing is they're staggering it. And staggering actually has a lot of implications on how you design, how you bring about the design. Firstly, you might think, well, that's going to be not as dense. And you're right, it isn't as dense as a true monolithic. But what it does do is allow you, you've got to deal with power and signals with transistors and how you connect them. When they're staggered, the power can come from one side or technically backside power and the signals can come from the top. When they're on top of each other, you've then got to go all the way around to connect them both. And that just makes it a lot more complicated. You tend to get slightly better density, but it's a lot more complicated in terms of connections. The other side of it is that the transistor performance can also depend on the width of the gate. And by doing it staggered, you can have wider gate widths just as just as a general rule.

[00:13:50]So putting that all together, IBM 7A nano stack is a staggered sequential C fet design using uh wafer onwafer bonding to bring over the latis, take off the carrier wafer and then build the transistors into that first lattice. Then after they do it, they actually turn it over and then do some more wiring. Uh what this produces, the numbers that they've got, and I'll bring them up here just to make sure I don't get them wrong, is uh they've seen that with this they can do a 50% logic area scaling, 50% performance at ISO power, 70% better efficiency at ISO performance, and 40% SRAMM scaling. And they say that this is doubling the amount of transistors per square millimeter compared to their 2nm gate allaround design they announced back in 2021.

[00:14:42]So this means it's 666 million transistors per square millm. Actually if you go see my article over on the substack I'll say that if you use the right numbers that 333 number I published many years ago should actually be about 270. So realistically this is more like 540 million transistors per square millimeter which is still more than double what the leading edge uh gay allaround products can do today. Now, the key element to all of this is in the bonding technology of bringing the two wafers together because recently we've done a number of pieces of content on Huawei and their logic stacking and they're bringing essentially two chiplets together and then them including all of the transistors on both chiplets into the density metric. And I said that was wrong even if they're doing it on a logic level. The reason why I said it was wrong is because the way they're bonding is through is using a technique called through silicon v. This is where you have copper pillars between your first and your uh second wafer. This is what AMD does when it's using vcash.

[00:15:53]This is what uh Intel is doing with fauos.

[00:15:57]The using copper pillars to join them means that yes, you can do signals, you can do power, but IBM isn't doing that. In essence, they don't need to bond with much accuracy at all. So when you talk hear about hybrid bonding on like the nine micron or six micron with an overlay accuracy of, you know, one micron, IBM doesn't have to worry here because the way that they're doing the bonding means that it doesn't ultimately matter how they bond it and where the overlay accuracy is. as long as the two wafers aren't like miles apart, you end up building the transistors and the connections into that latice you've transferred over. So your limit in your connections between the two simply become the limits in what you can do in lithography and in etching and in what you can do with high aspect ratio through uh as you put the the uh connections through the silicon. So technically they are through silicon vs but not in the way that we regularly talk about with hybrid bonding and that's where this all comes together and that's where IBM from a density perspective this is more um more real in terms of how we typically consider density compared to what Huawei is doing. What IBM says is the technology that they developed to enable that wafer on wafer bonding to get that bonding oxide that you have to have between the two wafers down to 30 nanometers or sub 30 nmters. That's the secret source and that's the one thing that we kept asking them about that they wouldn't tell us anything about because they say that's where the key innovation lies in all of this technology. Otherwise, realistically, you are just building gate all around transistors. And yes, there's innovation to do it at low temperature as well, but it's really that bonding that enables it all to work. Um, and ultimately, if it turns out that the other fabs seem to be going down the monolithic complimentary fat route rather than a sequential complimentary fat route. However, if this technology does get licensed and does take off, it will probably be that bonding element um that matters the most. And again in the substack I go through a number of more details about how um they do they enable that bonding oxide layer and how it's you know so flat and how they measure it with acoustic spectroscopy. It's all very interesting. The end of the day what IBM have here and you've probably seen the pictures of the chip already through the video that chip is not like a CPU. What these companies do in research is they develop test vehicles. So these are things like adders, oscillators, uh inverters, uh minor combinatorial logic into the silicon first just to see if it works. And that's why these chips look kind of irregular because all they're doing is testing lots of different things with the technology before you eventually get to a point where you can build chips with it. The other angle I haven't really covered here in this video, again it's in the substack, is the fact that modern chip design tools, what we call EDA, you may have heard of Synopsis and Cadence that and Seammens, like the two two and a half big companies that do EDA software and uh multifysics simulation.

[00:19:11]They are a few years behind in having the software ready to develop chips with this sort of technology. the fact that you have stacked transistors and staggered transistors. When we asked IBM about the development kits if you were to build chips on this with your cadence and your synopsis, uh they pointed out that actually the physical side of things, you know, like bonding and warpage and the thermals because you've now got transistors on top of each other are becoming a critical part in the design flow where they perhaps previously haven't in other generations. Yes, they matter a lot in chiplets, but not necessarily in the transistor layout. And now moving forward, that's going to have to be taken into consideration as these development kits are built. Now, it's been a long time since I went and visited IBM back at the Albany Nanoch facility. Um, as I understand it, the so they partnered with Albany Nanoch and they're in the process of installing a high NA high NA EUV machine. Uh, but like I say, it's been a few years since I visited. So ch the chances are that I'm going to invite myself over to come see them soon uh to get uh hands-on with this new 7A nanostack technology. Um see how it tastes. Um but if you want to see my other videos that I filmed about IBM while I was at Albany last time, there'll be links up and around. Um so what do you think of IBM 7A Nano Stack?

[00:20:42]Is it real? Do you have any questions?

[00:20:44]If if so, let me know down below. And if I get a chance to be in front of an executive, um, I'll put them to him or her and see what's going on. But thank you all for watching. And this is why I get up in the morning.