Why Die and Package Must Be Co‑Designed in Modern Chips #cadence #chipdesign #pcbdesign

追加: 2026-04-30

[00:00:00]The chip package refers to the physical housing that contains the chip and connects it to the circuit board. Chip package co-design means using die and package models. While the package model is included to boost the accuracy of the onchip analysis, the die model is added post the analysis. So to optimize the package in the chip design flow, you would be running decap optimization, power switch optimization, IR drop timing and SIA optimization.

[00:00:28]From the package design model, chip package resonance, noise analysis, and the EM analysis would be done. The onchip IR drop analysis tool interfaces with Algro package design. Sigerty package electrical analysis also interfaces using the MCP format which is very useful in mapping the board level pins to the chip level pins.