Did China just beat Intel?

[00:00:00]Right now, the world of semiconductor manufacturing is divided into those who have access to EUV lithography and those who don't. Losing access to EUV was a clear disadvantage for China, but how big is the manufacturing gap really?

[00:00:18]This is the HiSilicon Kirin 9030, the chip inside Huawei's newest flagship phone. A few weeks ago, we cut it open, put it under an electron microscope, and measured the smallest wires inside a chip, the metal pitch. And what we saw was unexpected. The smallest metal pitch inside the Kirin 9030 measures only 32.5 nanometers. That's smaller than the metal pitch in Pandalake, which is based on Intel's brand new 18A node. A Chinese fab, cut off from the most advanced tools, without EUV, is packing its wires about 10% tighter than Intel's leading edge EUV node. What's going on here? In this video, we'll figure out how SMIC pulled this off without EUV, why tighter wires doesn't always mean better, and why even being years behind, China is starting to become a big player at the fab table. But first, let's talk about where these numbers and measurements actually come from, because it's something really cool. We built a teardown lab, and with we, I mean SemiAnalysis. It's called STEEL, short for SemiAnalysis Teardown Engineering and Evaluation Lab. And teardown is exactly what it sounds like. You physically take apart the world's most advanced chips and reverse engineer how they were made. For about 20 years, doing that at scale was basically a one-company job, but not anymore. So, everything you're about to see, the cross-sections, the wire pitches, the transistor counts, comes directly from STEEL.

[00:01:57]The chip on the operating table is the Kirin 9030, Huawei's flagship SOC built on SMIC's third generation 7 nanometer process, internally called N+3.

[00:02:09]The most advanced process in China right now.

[00:02:11]But a number on its own doesn't tell you anything. You need something to compare it to. That's why Steel tore down a second chip right alongside it, the MediaTek Helio G99, a cheap budget phone SOC built on TSMC's N6. The [snorts] reason for that is simple. TSMC's N6 and SMIC's 7 nanometer N+3 are in the same ballpark, same kind of class of node.

[00:02:36]One made with the West's best equipment and one made in China under export controls. The idea is if we put them under the same microscope, the results hopefully tell us the whole story.

[00:02:47]Before we talk about the headline, the comparison with Intel's latest 18A, let's take a look at N3 versus N6. Does SMIC's N+3 achieve a tighter metal pitch than N6? The simple answer is yes, it does. The lowest metal pitch inside the Kirin 9030 measures at 32.5 nanometers, while the smallest metal pitch inside the N6 based Helio G99 comes in at 40 nanometers, a quite sizable difference.

[00:03:16]But tighter wires is a statement about density, about how much logic you can cram into a square millimeter, and not about how good or bad a chip or a process node is in general.

[00:03:27]And the minimum metal pitch, that's what we are talking about, is only one part of the equation.

[00:03:33]It is not a statement about how fast that logic switches or how little power it burns. When it comes to pure density, SMIC genuinely pulled it off. N+3 comes in at about 113 million transistors per square millimeter, while TSMC's N6 sits at about 108 million. So yes, SMIC's latest DUV node is actually denser than an EUV node.

[00:03:58]But, how do you hit EUV class density without EUV? There are two tricks, and both come with their own downsides. The first one is multi-patterning.

[00:04:08]EUV lets you print a relatively fine pattern in roughly one shot. Without EUV, we have to be more creative. The way it works is you start by printing a coarse pattern, depositing thin spacers along the edges, then you etch, and then you use those spacers as a brand new finer mask. It's a bit like drawing one line, tracing both of its edges to get two thinner lines, and then doing the exact same thing again. Do it once, and it's called self-aligned double patterning. Self-aligned because the spacers define themselves off the pattern that's already there. Do it twice, and it's quadruple patterning.

[00:04:45]SMIC's tightest layers need the quadruple version. And every extra pass is another mask, another alignment step, another chance to introduce an error, more cost, and of course, lower yields.

[00:04:59]And you know I don't like low yields.

[00:05:01]The second trick is DTCO, design technology co-optimization.

[00:05:06]DTCO means co-optimizing the whole chip design and the manufacturing technology together instead of treating them as separate problems. In practice, it's squeezing the cell layout itself. Fewer fins per transistor, landing the gate contact directly on top of the active gate instead of off to the side, or shrinking the isolation gaps between neighboring cells.

[00:05:29]Each DTCO trick claws back a little bit of area, but each one also makes the transistor a bit more delicate and a little harder to model. So, yes, SMIC matched a TSMC EUV node on density, but they got there by brute forcing DUV with more mask, more steps, and more ways to fail. That's not really a tie. And while the density looks generally impressive, it's also exactly where it starts to fall apart. Because area is the easy access to improve. Power and performance are much more difficult. Ever since Dennard scaling law died in the mid-2000s, that was the old rule named after Robert Dennard that simply shrinking a transistor makes it faster and more efficient, that free scaling is gone. And with DTCO, you have to fight for speed and efficiency separately.

[00:06:17]It's either or, not both at the same time. And this is exactly what we can see with SMIC's N+3 node.

[00:06:25]While the Kirin 9030 Pro is a relatively dense chip, it performs roughly like Android flagships from 3 years ago.

[00:06:31]Against today's best from Apple, Qualcomm, MediaTek, or Samsung, it's not even close. And the efficiency gap is even wider than the speed gap. The best example is Apple's tiny efficiency cores, the really small ones. Because Apple's E-cores beat Huawei's big prime core on integer performance. And they do so while drawing only about 1 W against 4.5 W for the big core A-core. In performance per clock, Huawei's prime core lands somewhere around an Arm Cortex-X2, a design from 2021.

[00:07:03]And honestly, that's respectable engineering. But Apple's M1 from 2020 is still around 35% faster per clock at similar power.

[00:07:12]And the current leading edge is multiple steps ahead of both. So yes, N+3 has a slight density advantage over TSMC's N6, but N6 is years old. Apple and Qualcomm are already building on N4 and N3, which are denser and sitting on a far better voltage frequency curve. And new N2-based chips will come later this year. They've got more transistors to spend, and every one of them switches faster at lower wattages. So SMIC kind of matched the wrong axis. The wires got smaller, the density increased, but the physics of the node did not catch up.

[00:07:48]And it's even more pronounced when we compare N+3 to Intel's latest 18A. On paper, 18A can achieve a M0 metal pitch of 32 nanometers, right on par with N+3.

[00:07:59]But on Pantal Lake, Intel makes heavy use of high-performance cells with a looser metal pitch of only 36 nanometers.

[00:08:07]Depending on your design goal, a more relaxed M0 metal pitch can also create advantages in cost and yield because it reduces complexity. But only if you have the freedom to decide how and where you scale, which means the tighter than Intel headline, while true, doesn't say anything about competitiveness. The number is real, it just isn't measuring the thing that decides who actually wins. And on transistor density, 18A clearly outclasses N+3, even with the slightly relaxed metal pitch. Because just like there's more to a chip than density, there's more to density than the M0 metal pitch.

[00:08:42]Backside power delivery actually allows you to lower the front side metal pitch because the power connectors come in from the backside of the chip. So, why is everyone still scared about China?

[00:08:52]Because being a few years behind is not the same as being stuck. And there's still room to grow for SMIC, even on DUV. Tighter lower metals, for example, M0 is just the first metal layer. After that, you have many more. Shorter cells, a tighter gate pitch.

[00:09:09]On paper, a future N+4 could roughly match TSMC's N5 class density, and N+5 with backside power delivery could get to Intel 18A class density. But again, only on density, not on power and performance. But, and that's the important part, the difficulty is cumulative. Every single one of those optimizations, on its own, is plausible, but stack them all without EUV, and each new node comes out slower, more expensive, and less forgiving than the last. You can keep climbing the wall, but the wall just keeps getting steeper.

[00:09:43]Export controls didn't stop China. They changed the problem China is solving.

[00:09:48]And the knowledge is spreading. SMIC is being directed to license N+2 and N+3 out to other domestic fabs. And if that process learning flows into AI accelerators, then the choke point stops being one single fab you can sanction and becomes an entire ecosystem. So, let's do a quick recap of SMIC's 7-nanometer N+3 node. No EUV, no backside power yet. Higher complexity, higher cost, and real efficiency gaps.

[00:10:16]By every measure that matters at the bleeding edge, China is not closing the distance to TSMC, Intel, and Samsung.

[00:10:23]That much is generally clear under the microscope.

[00:10:26]But behind the leading edge and irrelevant are two completely different things. If domestic chips get good enough for phones, for inference, for networking, for anything security-sensitive, it's a win. China doesn't have to be TSMC to matter. They just need to be good enough to not need TSMC at all.

[00:10:45]Everything in this video came out of Steel. Die annotation, block level analysis, electron microscope cross-sections cut straight through the logic and the memory. And there's a lot we had to skip in this video. The full process flow, the material analysis, fin measurements, the packaging breakdown.

[00:11:02]So, if you're interested in a real deep dive into SMIC's latest node, check out the SemAnalysis TechInsights article.

[00:11:09]No, really, check it out. It's pretty amazing. I put the link in the video description below.

[00:11:14]This is the first public report out of Steel and there is definitely more to come. Subscribe if this is the kind of work you want to see more of. I really like to know what you think on this one.

[00:11:25]Is good enough to not need TSMC actually good enough? Let me know in the the below.

[00:11:31]I hope you found this video interesting and see you in the next one.